參數(shù)資料
型號(hào)： ADUC7034BCPZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 92/136頁
文件大小： 0K
描述： IC MCU FLASH 32K ANLG IO 48LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲(chǔ)器容量： 32KB（16K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 115°C
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
ADuC7034
Rev. B | Page 59 of 136
ADC CALIBRATION
As shown in detail in the top-level diagrams (Figure 17 and
Figure 18), the signal flow through all ADC channels can be
described in as follows:
1.
An input voltage is applied through an input buffer (and
through PGA in the case of the I-ADC) to the Σ-Δ modulator.
2.
The modulator output is applied to a programmable digital
decimation filter.
3.
The filter output result is averaged if chopping is used.
4.
An offset value (ADCxOF) is subtracted from the result.
5.
The result is scaled by a gain value (ADCxGN).
6.
The result is formatted as twos complement/offset binary,
rounded to 16 bits, or clamped to ±full scale.
Each ADC has a specific offset and gain correction or calibra-
tion coefficient associated with it that is stored in MMR-based
offset and gain registers (ADCxOF and ADCxGN). The offset
and gain registers can be used to remove offsets and gain errors
within the part as well as system-level offset and gain errors
external to the part.
These registers are configured at power-on with a factory-
programmed calibration value. These factory-set calibration
values vary from part to part, reflecting the manufacturing
variability of internal ADC circuits. However, these registers
can also be overwritten by user code if the ADC is in idle mode
and are automatically overwritten if an offset or gain calibration
cycle is initiated by the user through the mode bits in the
ADCMDE[2:0] MMR. Two types of automatic calibration are
available to the user, namely, self-calibration or system calibration.
Self-Calibration
In self-calibration of offset errors, the ADC generates its
calibration coefficient based on an internally generated 0 V,
whereas in self-calibration of gain errors the coefficient is based
on the full-scale voltage. Although self-calibration can correct
offset and gain errors within the ADC, it cannot compensate for
external errors in the system, such as shunt resistor tolerance/drift
and external offset voltages.
Note that in self-calibration mode, ADC0GN must contain the
values for PGA = 1 before a calibration scheme is started.
System Calibration
In system calibration of offset errors, the ADC generates
its calibration coefficient based on an externally generated
zero-scale voltage, whereas in system calibration of gain errors
the coefficient is based on the full-scale voltage. The calibration
coefficient is applied to the external ADC input for the duration
of the calibration cycle.
The duration of an offset calibration is a single conversion cycle
(3/fADC chop off, 2/fADC chop on) before returning the ADC to
idle mode. A gain calibration is a two-stage process and, there-
fore, takes twice as long as an offset calibration cycle. When a
calibration cycle is initiated, any ongoing ADC conversion is
immediately halted, the calibration is automatically performed
at the ADC update rate programmed in ADCFLT, and the ADC
is always returned to idle after any calibration cycle. It is strongly
recommended that ADC calibration be initiated at as low an ADC
update rate as possible (and therefore requires a high SF value
in ADCFLT) to minimize the impact of ADC noise during
calibration.
Using the Offset and Gain Calibration
If the chop enable bit (ADCFLT[15]) is enabled, internal ADC
offset errors are minimized and an offset calibration may not be
required. If chopping is disabled, however, an initial offset
calibration is required and may need to be repeated, particularly
after a large change in temperature.
Depending on system accuracy requirements, a gain calibration,
especially in the context of the I-ADC (with internal PGA), may
need to be performed at all relevant system gain ranges. If it is
not possible to apply an external full-scale current on all gain
ranges, apply a lower current and then scale the result produced
by the calibration. For example, apply a 50% current and then
divide the ADC0GN value produced by 2 and write this value
back into ADC0GN. Note that there is a lower limit for the
input signal that can be applied during a system calibration
because ADC0GN is only a 16-bit register. The input span (that
is, the difference between the system zero-scale value and the
system full-scale value) should be greater than 40% of the
nominal full-scale input range (that is, >40% of VREF/gain).
The on-chip Flash/EE memory can be used to store multiple
calibration coefficients. These calibration coefficients can be
copied directly into the relevant calibration registers by user
code and are based on the system configuration. In general, the
simplest way to use the calibration registers is to let the ADC
calculate the values required as part of the ADC automatic
calibration modes.
A factory-programmed or end-of-line calibration for the I-ADC is
a two-step procedure:
1. Apply 0 A current. Configure the ADC in the required PGA
setting and write to ADCMDE[2:0] to perform a system
zero-scale calibration. This writes a new offset calibration
value into ADC0OF.
2. Apply a full-scale current for the selected PGA setting. Write
to ADCMDE to perform a system full-scale calibration. This
writes a new gain calibration value into ADC0GN.
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