參數(shù)資料
型號： ADUC7034BCPZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 103/136頁
文件大?。?/td> 0K
描述： IC MCU FLASH 32K ANLG IO 48LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 115°C
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
ADuC7034
Rev. B | Page 69 of 136
Normal Interrupt (IRQ) Request
The IRQ request is the exception signal allowed to enter the
processor in IRQ mode. It is used to service general-purpose
interrupt handling of internal and external events.
All 32 bits of the IRQSTA MMR are OR’ed to create a single
IRQ signal to the ARM7TDMI core. The four 32-bit registers
dedicated to IRQ are described in the IRQSIG to IRQSTA
sections.
IRQSIG Register
Name:
IRQSIG
Address:
0xFFFF0004
Default Value:
0x00000000
Access:
Read access only
Function:
This 32-bit register reflects the current state
of all IRQ sources. If a peripheral generates
an IRQ signal, the corresponding bit in the
IRQSIG is set; otherwise, the corresponding
bit is cleared. The IRQSIG bits are cleared
when the interrupt in the peripheral is cleared.
All IRQ sources can be masked in the IRQEN
MMR.
IRQSTA Register
Name:
IRQSTA
Address:
0xFFFF0000
Default Value:
0x00000000
Access:
Read only
Function:
IRQSTA provides the status of the IRQ source
that is currently enabled (that is, a logic AND
of the IRQSIG and IRQEN bits). When a bit
in this register is set to 1, the corresponding
source generates an active IRQ request to the
ARM7TDMI core. There is no priority encoder
or interrupt vector generation. This function
is implemented in software in a common
interrupt handler routine.
IRQEN Register
Name:
IRQEN
Address:
0xFFFF0008
Default Value:
0x00000000
Access:
Read/write
Function:
IRQEN provides the value of the current enable
mask. When a bit is set to 1, the corresponding
source request is enabled to create an IRQ
exception signal. When a bit is set to 0, the
corresponding source request is disabled or
masked and does not create an IRQ exception
signal. The IRQEN register cannot be used to
disable an interrupt.
IRQCLR Register
Name:
IRQCLR
Address:
0xFFFF000C
Access:
Write only
Function:
IRQCLR allows the IRQEN register to clear in
order to mask an interrupt source. Each bit set to 1
clears the corresponding bit in the IRQEN register
without affecting the remaining bits. When used as
a pair of registers, IRQEN and IRQCLR allow
independent manipulation of the enable mask
without requiring an atomic read-modify-write
instruction.
Fast Interrupt (FIQ) Request
The FIQ request is the exception signal allowed to enter the
processor in FIQ mode. It is provided to service data transfer or
communication channel tasks with low latency. The FIQ
interface is identical to the IRQ interface and provides the
second-level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.
All 32 bits of the FIQSTA MMR are OR’ed to create the FIQ
signal to the core and to Bit 0 of both the FIQ and IRQ registers
(FIQ source).
The logic for FIQEN and FIQCLR does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. As a side effect, a
bit set to 1 in FIQEN clears the same bit in IRQEN. Likewise, a
bit set to 1 in IRQEN clears the same bit in FIQEN. An interrupt
source can be disabled in both IRQEN and FIQEN masks.
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