參數(shù)資料
型號： ADUC7034BCPZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 23/136頁
文件大?。?/td> 0K
描述： IC MCU FLASH 32K ANLG IO 48LFCSP
標準包裝： 2,500
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 115°C
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
ADuC7034
Rev. B | Page 119 of 136
LIN Hardware Synchronization Control Register 0
Name:
LHSCON0
Address:
0xFFFF0784
Default Value:
0x0000
Access:
Read/write
Function:
The LHS control register is a 16-bit register that is used in conjunction with the LHSCON1 register to configure the LIN
mode of operation.
Table 92. LHSCON0 MMR Bit Designations
Bit
Description
16 to 13
Reserved. These bits are reserved for future use and should be written as 0 by user software.
12
Rising edge detected interrupt disable.
Mode
Description
BSD Mode
Set to 1 to disable the rising edge detected interrupt.
Cleared to 0 to enable the break rising edge detected interrupt.
LIN Mode
Set to 1 to enable the rising edge detected interrupt.
Cleared to 0 to disable the break rising edge detected interrupt.
11
Break timer compare interrupt disable.
Set to 1 to disable the break timer compare interrupt.
Cleared to 0 to enable the break timer compare interrupt.
10
Break timer error interrupt disable.
Set to 1 to disable the break timer error interrupt.
Cleared to 0 to enable the break timer error interrupt.
9
LIN transceiver, standalone test mode.
Set to 1 by user code to enable external GPIO_7 and GPIO_8 pins to drive the LIN transceiver TxD and LIN transceiver RxD,
respectively, independent of the UART. The functions of GPIO_7 and GPIO_8 should first be configured by user code via the GPIO
Function Select Bit 0 and GPIO Function Select Bit 4 in the GP2CON register.
Cleared to 0 by user code to operate the LIN in normal mode; it is driven directly from the on-chip UART.
8
Gate UART/BSD R/W bit.
Mode
Description
UART Mode
Set to 1 by user code to disable the internal UART RxD (receive data) by gating it high until both the
break field and the subsequent LIN sync byte are detected. This ensures that during break or sync field
periods the UART does not receive any spurious serial data, which would have to be flushed out of the
UART before valid data fields could be received.
Cleared to 0 by user code to enable the internal UART RxD (receive data) after the break field and the
subsequent LIN sync byte have been detected so that the UART can receive the subsequent LIN data fields.
BSD Read Mode1
Set to 1 by user code to enable the generation of a break condition interrupt (LHSSTA[0]) on a rising
edge of the BSD bus. The break timer (LHSVAL1) starts counting on the falling edge and stops counting
on the rising edge, where an interrupt is generated, allowing user code to determine if a 0, 1, or sync
pulse width has been received. The break timer generates an interrupt if the value in the LIN break timer
(LHSVAL1 read value) equals the break timer compare value (LHSVAL1 write value) and if the break timer
overflows. This configuration can be used in BSD read mode to detect fault conditions on the BSD bus.
BSD Write Mode1
Cleared to 0 by user code to disable the generation of break condition interrupts on a rising edge of the
BSD bus. The LHS compare interrupt (LHSSTA[3]) is used to determine when the MCU should release the
BSD bus when transmitting data. If the break condition interrupt is still enabled, it generates an unwanted
interrupt as soon as the BSD bus is deasserted. As in BSD read mode, the break timer stops counting on
a rising edge; therefore, the break timer can also be used in this mode to allow user code to confirm the
pulse width in transmitted data bits.
7
Sync timer stop edge type bit.
Set to 1 by user code to stop the sync timer on the rising edge count configured through the LHSCON1[7:4] register.
Cleared to 0 by user code to stop the sync timer on the falling edge count configured through the LHSCON1[7:4] register.
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