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| 型號： | ADUC7034BCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 126/136頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 32K ANLG IO 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲器容量： | 32KB（16K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 115°C |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7034
Rev. B | Page 9 of 136
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
POWER REQUIREMENTS
Power Supply Voltages
VDD (Battery Supply)
3.5
18
V
REG_DVDD, REG_AVDD33
2.5
2.6
2.7
V
Power Consumption
MCU clock rate = 10.24 MHz, ADC off
10
20
mA
MCU clock rate = 20.48 MHz, ADC off
20
mA
ADC low power mode, measured over the
range of TA = 10°C to +40°C, continuous ADC
conversion
300
400
μA
ADC low power mode, measured over the
range of TA = 40°C to +85°C, continuous ADC
conversion
300
500
μA
ADC low power plus mode, measured over an
ambient temperature range of TA = 10°C to
+40°C, continuous ADC conversion
520
700
μA
Average current, measured with wake-up and
watchdog timer clocked from the low power
oscillator, TA = 40°C to +85°C
120
300
μA
IDD (MCU Powered Down)
Average current, measured with wake-up and
watchdog timer clocked from low power
oscillator over a range of TA = 10°C to +40°C
120
175
μA
IDD (Current ADC)
1.7
mA
IDD (Voltage/Temperature ADC)
0.5
mA
IDD (Precision Oscillator)
400
μA
1 These numbers are not production tested, but are guaranteed by design and/or characterization data at production release.
2 Valid for a current channel ADC PGA setting of 4 to 64.
3 These numbers include temperature drift.
4 Tested at a gain range of 4; self-offset calibration removes this error.
5 Measured with an internal short after an initial offset calibration.
6 Measured with an internal short.
7 These numbers include internal reference temperature drift.
8 Factory calibrated at a gain of 1.
9 System calibration at a specific gain range (and temperature) removes the error at this gain range (and temperature).
10 Includes an initial system calibration.
11 Using ADC normal mode voltage reference.
12 Typical noise in low power modes is measured with chop enabled.
13 Voltage channel specifications include resistive attenuator input stage.
14 System calibration removes this error at the specified temperature.
15 RMS noise is referred to the voltage attenuator input (for example, at fADC = 1 kHz, typical rms noise at the ADC input is 7.5 μV) and scaled by the attenuator (divide-by-24)
to yield these input-referred noise figures.
16 Valid after an initial self-calibration.
17 In ADC low power mode, the input range is fixed at ±9.375 mV. In ADC low power plus mode, the input range is fixed at ±2.34375 mV.
18 It is possible to extend the ADC input range by up to 10% by modifying the factory-set value of the gain calibration register or by using system calibration. Extending
the ADC input range can also be used to reduce the ADC input range (LSB size).
19 Limited by minimum/maximum absolute input voltage range.
20 Valid for a differential input less than 10 mV.
21 Measured using the box method.
22 The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
23 References of up to REG_AVDD can be accommodated for by enabling an internal divide-by-2.
24 Die temperature.
25 Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at 40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.
26 Retention lifetime equivalent at a junction temperature (TJ) of 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.
27 Low power oscillator can be calibrated against either the precision oscillator or the external 32.768 kHz crystal in user code.
28 These numbers are not production tested, but are supported by LIN compliance testing.
29 BSD electrical specifications, except high and low voltage levels, are per LIN 2.0 with pull-up resistor disabled and CLoad = 10 nF maximum.
30 This specification does not apply directly to the WU pin but includes an RLIMIT of 39 Ω on the wake-up line.
31 In response to a thermal shutdown event, the MCU core is not shut down but is interrupted, and the high voltage I/O pins are disabled.
32 Thermal impedance can be used to calculate the thermal gradient from ambient to die temperature.
33 Internal regulated supply available at REG_DVDD (ISOURCE = 5 mA) and REG_AVDD (ISOURCE = 1 mA).
34 The specification listed is typical; additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively.
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