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參數(shù)資料
| 型號： | ADUC7034BCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 55/136頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 32K ANLG IO 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲器容量： | 32KB（16K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 115°C |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7034
Rev. B | Page 25 of 136
FLASH/EE MEMORY
The ADuC7034 incorporates Flash/EE memory technology on
chip to provide the user with nonvolatile, in-circuit
reprogrammable memory space.
Like EEPROM, Flash memory can be programmed in-system at
a byte level, although it must first be erased, with the erasure being
performed in page blocks. Therefore, Flash memory is often
and more correctly referred to as Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes nonvolatility, in-circuit program-
mability, high density, and low cost. Incorporated within the
ADuC7034, Flash/EE memory technology allows the user to
update program code space in-circuit without the need to
replace one-time programmable (OTP) devices at remote
operating nodes.
The Flash/EE memory is physically located at Address 0x80000.
Upon a hard reset, the Flash/EE memory maps to Address
0x00000000. The factory-set default contents of all Flash/EE
memory locations is 0xFF. Flash/EE can be read in 8-/16-/32-bit
segments and written in segments of 16 bits. The Flash/EE is
rated for 10,000 endurance cycles. This rating is based on the
number of times that each byte is cycled, that is, erased and
programmed. Implementing a redundancy scheme in the
software ensures greater than 10,000 endurance cycles.
The user can also write data variables to the Flash/EE memory
during run-time code execution, for example, for storing
diagnostic battery parameter data.
The entire Flash/EE is available to the user as code and non-
volatile data memory. There is no distinction between data
space and program space during ARM code processing. The
real width of the Flash/EE memory is 16 bits, meaning that in
ARM mode (32-bit instruction), two accesses to the Flash/EE
are necessary for each instruction fetch. When operating at
speeds of less than 20.48 MHz, the Flash/EE memory controller
can transparently fetch the second 16-bit halfword (part of the
32-bit ARM operation code) within a single core clock period.
Therefore, for speeds less than 20.48 MHz (that is, CD > 0), it is
recommended to use ARM mode. For 20.48 MHz operation
(that is, CD = 0), it is recommended to operate in Thumb mode.
The page size of this Flash/EE memory is 512 bytes. Typically,
it takes the Flash/EE controller 20 ms to erase a page, regardless
of CD. Writing a 16-bit word at CD = 0, 1, 2, or 3 requires 50 μs;
at CD = 4 or 57, 0 μs; at CD = 6, 80 μs; and at CD = 7, 105 μs.
It is possible to write to a single 16-bit location only twice
between erasures; that is, it is possible to walk bytes, not bits.
If a location is written to more than twice, the contents of the
Flash/EE page may become corrupt.
PROGRAMMING FLASH/EE MEMORY IN-CIRCUIT
The Flash/EE memory can be programmed in-circuit, using a
serial download mode via the LIN interface or the integrated
JTAG port.
Serial Downloading (In-Circuit Programming)
The ADuC7034 facilitates code download via the LIN pin.
JTAG Access
The ADuC7034 features an on-chip JTAG debug port to
facilitate code downloading and debugging.
ADuC7034 Flash/EE Memory
The total 32 kB of Flash/EE is organized as 15,000 × 16 bits. Of
this total, 30 kB are user space and 2 kB are reserved for boot
loader/kernel space.
FLASH/EE CONTROL INTERFACE
Access to and control of the Flash/EE memory on the
ADuC7034 is managed by an on-chip memory controller. The
controller manages the Flash/EE memory as a single block of 32 kB.
It should be noted that the MCU core is halted until the
command completes. User software must ensure that the
Flash/EE controller completes any erase or write cycle before
the PLL is powered down. If the PLL is powered down before an
erase or write cycle is completed, the Flash/EE page may become
corrupt. User code, LIN, and JTAG programming use the Flash/EE
control interface, consisting of the following MMRs:
FEE0STA: read only register. Reflects the status of the
Flash/EE control interface.
FEE0MOD: sets the operating mode of the Flash/EE
control interface.
FEE0CON: 8-bit command register. The commands are
interpreted as described in Table 13.
FEE0DAT: 16-bit data register.
FEE0ADR: 16-bit address register.
FEE0SIG: holds the 24-bit code signature as a result of the
signature command being initiated.
FEE0HID: protection MMR. Controls read and write
protection of the Flash/EE memory code space. If
previously configured via the FEE0PRO register, FEE0HID
may require a software key to enable access.
FEE0PRO: a buffer of the FEE0HID register. Stores the
FEE0HID value and therefore automatically downloads to the
FEE0HID registers on subsequent reset and power-on events.
The FEE0CON Register to FEE0DAT Register sections provide
detailed descriptions of the bit designations for each of the
Flash/EE control MMRs.
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