參數(shù)資料
型號(hào): μPD30100
廠商: NEC Corp.
英文描述: 64-bit RISC Microprosessor(64位 RISC 微處理器)
中文描述: 64位RISC Microprosessor(64位的RISC微處理器)
文件頁(yè)數(shù): 9/52頁(yè)
文件大?。?/td> 365K
代理商: ΜPD30100
9
μ
PD30100
(6) Data cache
The following methods are employed:
Direct map
Virtual index address
Physical tag, write back cache
The capacity of the data cache is 1K byte.
Each cache line consists of 4-word data and its byte parity, 22-bit tag and its parity bit, valid bit, write back bit
and its parity bit.
(7) System interface
This interface enables the processor to access external resources to satisfy internal requests.
The system interface consists of a 32-bit multiplexed address/data bus, clock signal, interrupt, and control signal.
(8) Clock generator
Generates the following four clocks from the input clock (MasterClock):
PClock
MasterOut : Clock output to external agent in synchronization with MasterClock
SClock
: System interface clock (internal). Two frequencies can be selected at cold reset
TClock
: Output clock as reference for external agent. Same frequency as SClock
: Pipeline clock (internal)
The clocks internally generated by the processor can be temporarily stopped by a power mode.
The V
R
4100 uses a phase locked loop (PLL) to suppress skew between the input clock and internal clock.
相關(guān)PDF資料
PDF描述
μPD30101 64-Bit Microprocessor(64位微處理器)
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μPD30121 64-Bit MIPS RISC Microprocessor(64 位RISC 微處理器)
μPD30122 64-Bit RISC Microprosessor(64位RISC微處理器)
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