參數(shù)資料
型號(hào)： μPD30100
廠商： NEC Corp.
英文描述： 64-bit RISC Microprosessor(64位 RISC 微處理器)
中文描述： 64位RISC Microprosessor（64位的RISC微處理器）
文件頁(yè)數(shù)： 29/52頁(yè)
文件大?。?/td> 365K
代理商： ΜPD30100
29
μ
PD30100
Figure 4-1. Processor Block Read Request and the Following Read Response
1
2
3
4
5
6
7
8
9
10
11
12
SCycle
SClock
(Internal)
SysAD (31 : 0)
(I/O)
SysCmd (4 : 0)
(I/O)
PValid
(Output)
PMaster
(Output)
EReq
(Input)
ERdy
(Input)
EValid
(Input)
Addr
Read
Data0
Data
Data1
Data
Data2
Data
Data3
EOD
Hi-Z
Hi-Z
H
Hi-Z
Hi-Z
4.1.2 Control of data transfer rate
The system interface of the V
R
4100 can transfer word data in one cycle.
The external agent can transfer data to the processor at any transfer rate. The rate at which data is
transferred from the processor to the external agent is set by the EP field of the config register. The V
R
4100
has four write data transfer rates: “D”, “DX”, “DXX”, and “DXXX”. The processor holds the data output during
the period “D” immediately before, during the period of “X”, and continues output.
The pattern of the data transfer rate is expressed by a combination of symbols “D” and “X”, where “D”
indicates the data transfer cycle, and “X” indicates an unused cycle. This transfer pattern indicates an
appropriate data transfer rate by a data cycle and unused cycle.
Example
DXX: Transfers 1-word data every 3 cycles
Figure 4-2 shows the timing of the processor block write request when the transfer pattern is DXX.
Figure 4-2. Processor Block Write Request When Transfer Pattern Is DXX
SCycle
SClock (internal)
SysAD (31:0)
(I/O)
SysCmd (4:0)
(I/O)
PValid (output)
10
11
12
9
8
7
6
5
4
3
2
1
PMaster (output)
ERdy (input)
Data0
Data
Addr
Write
L
Data1
EOD
Undefined
Data0 Data0
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