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參數(shù)資料
| 型號： | μPD30100 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-bit RISC Microprosessor(64位 RISC 微處理器) |
| 中文描述： | 64位RISC Microprosessor（64位的RISC微處理器） |
| 文件頁數(shù)： | 30/52頁 |
| 文件大?。?/td> | 365K |
| 代理商： | ΜPD30100 |
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30
μ
PD30100
4.1.3 Clock interface
The internal clock of the V
R
4100 is controlled by an internal phase lock loop (PLL) circuit. This PLL circuit
synchronizes the internal clock of the V
R
4100 with the MasterClock (input clock) signal.
Stopping the output of the clock can be controlled in the power mode. For details, refer to
3.1 POWER
MODES
.
The clock signals used in the V
R
4100 are described below.
(1) MasterClock (Input)
All internal clocks and external clocks are generated based on the MasterClock.
(2) PClock (Internal)
PClock is the basis of the pipeline operation. The frequency of PClock is 4 times higher than that of the Master
Clock.
(3) SClock (Internal)
SClock is the basis of the operation of the system interface. However, this clock does not output to the external
agent.
SClock is generated by dividing PClock. The division ratio to generate the SClock from the PClock is set by the
Div2 pin at cold reset.
Div2
PClock : SClock (Frequency Ratio)
0
2 : 1
1
1 : 1
(4) TClock (Output)
TClock is the clock on which the operation of external agents is based.
TClock is generated at the same frequency as that of SClock, and is synchronized with SClock.
(5) MasterOut (Output)
MasterOut is generated at the same frequency as MasterClock and is synchronized with MasterClock.
This clock is used for the external logic that controls resets or interrupts.
Figure 4-3. Clock Interface
MasterClock
PLL
PClock
Internal device
SClock
TClock
System
interface
To external agent
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| PD301-024-03-PI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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