
13
μ
PD30100
3.3 CPU Register
3.3.1 Overview of register file
Figure 3-4 shows the CPU registers of the VR4100. The bit width of these registers is determined by the
operation mode of the processor (in 32-bit mode: 32 bits, in 64-bit mode: 64 bits).
Of the thirty-two general-purpose registers of the V
R
4100, the following two registers have special meanings:
Register r0
:
The contents of this register are always 0. To discard the result of an operation, this register
can be coded as the target of the instruction. If the value 0 is needed, this register can be
used as a source register.
This is a link register for the JAL and JALR instructions. Therefore, do not use this register
with any other instructions.
Register r31 :
The two multiplication/division registers (HI and LO) store the result of multiplication or sum-of-products
operation, or quotient (LO) and remainder (HI) resulting from division.
However, because the V
R
4100 does not support floating-point operation instructions, the thirty-two floating-
point general-purpose registers (FGRs), which are provided in the V
R
4200
and V
R
4400
, are not provided in
the V
R
4100.
Remark
The load link bit (LL bit) used for the multi-processor system synchronization instructions (LL and SC)
supported by the V
R
4200 and V
R
4400 is not provided in the V
R
4100 (refer to
3.4 (2) Deletion of multi-
processor instructions
).
Figure 3-4. CPU Registers
63
0
r0 = 0
r1
r2
.
.
.
.
r29
r30
r31 (link address)
General-purpose registers
63
0
Multiplication/division registers
HI
63
0
LO
63
0
PC
Program counter
No program status word (PSW) is provided. The function of the program status word is substituted by the
status register and cause register of the system control coprocessor (CP0).