
49
μ
PD30100
APPENDIX DIFFERENCES BETWEEN V
R
4100 AND V
R
4300
TM
Item
V
R
4100
V
R
4300
Instruction
set
Multi-processor synchronization
(LL, LLD, SC, SCD) instructions
None
Supported
Sum-of-products (MADD16,
DMADD16) Instructions
Supported
None
Standby mode transition
instruction
Supported
None
Floating-point instruction
None
Supported
PRld register
Imp = 0x0C
Imp = 0x0B
TLB
Page size
1 K, 4 K, 16 K, 64 K, 256 K
4 K, 16 K, 64 K, 256 K, 1 M, 4 M, 16 M
Cache
Size
Instruction: 2K bytes
Data: 1K bytes
Instruction: 16K bytes
Data: 8K bytes
Line size
Instruction: 4 words
Data: 4 words
Instruction: 8 words
Data: 4 words
Parity
Instruction: 1 bit per 1 word
Data: 1 bit per 1 byte
None
System bus
Handshake signal
EReq, PReq, PMaster, ERdy
EReq, PReq, PMaster, EOK
interface
Write data transfer rate
D, Dx, Dxx, Dxxx
D, Dxx
Address generation during
block read
Subblock in word units for both
instruction and data
Instruction: Sequential
Data: Subblock in 2-word units
Address generation during
block write
Subblock in word units for both
instruction and data
Sequential for both instruction and data
Non-cache high-speed write
Supported (set by AD bit of config
register)
Supported
Address ready timing
2S cycles before issuance cycle
(ERdy active)
From 1S cycle before issuance cycle
to issuance cycle (EOK active)
Re-execution of processor
request
None
Supported
Status after last data write
Ends access
Retains last data when transfer rate
is set
Parity check
1 bit per 1 byte
None
SysCmd bus parity miss
indication
Fault pin
None
Clock
interface
Multiplication rate of input to
internal
4
1.5, 2, 3
Division rate of internal to bus
1, 2
1.5, 2, 3
Clock output
TClock, MasterOut
TClock
SyncOut-SyncIn bus
None
Supported
Manipulation at cold reset
Both ColdReset and Reset pins are
asserted
ColdReset pin is asserted (Reset pin
is don’t care)
JTAG interface
None
Supported
Standby mode
3 types
None
Supply voltage
2.2 to 3.6 V
3.0 to 3.6 V