參數(shù)資料
型號(hào)： μPD30100
廠商： NEC Corp.
英文描述： 64-bit RISC Microprosessor(64位 RISC 微處理器)
中文描述： 64位RISC Microprosessor（64位的RISC微處理器）
文件頁(yè)數(shù)： 25/52頁(yè)
文件大?。?/td> 365K
代理商： ΜPD30100
25
μ
PD30100
Figure 3-18. Format of Data Cache
128 127
144 143
165
169 168
167 166
8
0
1
1
1
1
22
16
128
PTag
DataP
Data
0
W’
W
P
V
W’
W
P
V
PTag : Physical tag (bits 31 through 10 of physical address)
DataP : Even parity for data (parity of 1 bit per 1-byte data)
Data
: Cache data
: Even parity for write back bit
: Write back bit
: Even parity for physical tag and V bit
: Valid bit
3.9 Exception Processing
If an exception occurs, the V
R
4100 enters the kernel mode with interrupts disabled, and executes an
exception handler from a fixed exception vector address. When execution returns from the exception handler,
it is necessary to restore the original information on the program counter, operating mode, and enabling of
interrupts. Therefore, save this information when an exception occurs.
When an exception occurs, the EPC register holds the address of the instruction that has generated the
exception. If the exception occurs in the delay branch slot, the EPC register holds the address of the instruction
immediately before the instruction that has generated the exception. In other words, the EPC register stores
an address from which execution is to be started after exception processing has been completed. The V
R
4100
also has the following modes related to exception processing. At reset, the restart address is retained when
the NMI is generated.
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