
36
μ
PD30100
Table 6-1. CPU Instruction Set: ISA (3/3)
Instructions
Description
Format
Coprocessor instruction (3)
COPz
Coprocessor z Operation
COPz
cofun
Coprocessor instruction (4)
BCzT
Branch On Coprocessor z True
BCzT
offset
BCzF
Branch On Coprocessor z False
BCzF
offset
COPz
CO
cofun
COPz
BC
br
offset
Table 6-2. CPU Instruction Set: Expansion ISA (1/2)
op
base
rt
offset
op
rs
rt
immediate
op
rs
rt
rd
sa
funct
op
rs
rt
rd
sa
funct
Instructions
Description
Format
Load/store instruction
LD
LDL
LDR
LWU
SD
SDL
SDR
ALU immediate instruction
DADDI
DADDIU
3-operand type instruction
DADD
DADDU
DSUB
DSUBU
Shift instruction
DSLL
DSRL
DSRA
DSLLV
DSRLV
DSRAV
DSLL32
DSRL32
DSRA32
Load Doubleword
Load Doubleword Left
Load Doubleword Right
Load Word Unsigned
Store Doubleword
Store Doubleword Left
Store Doubleword Right
Doubleword Add Immediate
Doubleword Add Immediate Unsigned
Doubleword Add
Doubleword Add Unsigned
Doubleword Subtract
Doubleword Subtract Unsigned
Doubleword Shift Left Logical
Doubleword Shift Right Logical
Doubleword Shift Right Arithmetic
Doubleword Shift Left Logical Variable
Doubleword Shift Right Logical Variable
Doubleword Shift Right Arithmetic Variable
Doubleword Shift Left Logical +32
Doubleword Shift Right Logiscal +32
Doubleword Shift Right Arithmetic +32
LD
LDL
LDR
LWU
SD
SDL
SDR
DADDI
DADDIU
DADD
DADDU
DSUB
DSUBU
DSLL
DSRL
DSRA
DSLLV
DSRLV
DSRAV
DSLL32
DSRL32
DSRA32
rt, offset (base)
rt, offset (base)
rt, offset (base)
rt, offset (base)
rt, offset (base)
rt, offset (base)
rt, offset (base)
rt, rs, immediate
rt, rs, immediate
rd, rs, rt
rd, rs, rt
rd, rs, rt
rd, rs, rt
rd, rt, sa
rd, rt, sa
rd, rt, sa
rd, rt, rs
rd, rt, rs
rd, rt, rs
rd, rt, sa
rd, rt, sa
rd, rt, sa