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參數(shù)資料
| 型號： | μPD30100 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-bit RISC Microprosessor(64位 RISC 微處理器) |
| 中文描述： | 64位RISC Microprosessor（64位的RISC微處理器） |
| 文件頁數(shù)： | 28/52頁 |
| 文件大小： | 365K |
| 代理商： | ΜPD30100 |
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28
μ
PD30100
4. INTERFACES
4.1 System Interface
There are the following four system interface buses.
SysAD (31:0) : Bus for address and data transfer.
SysADC (3:0) : Even parity bus for SysAD bus.
SysCmd (4:0) : Bus for command and data identifier transfer.
SysCmdP
: Even parity bit for SysCmd bus
The SysAD and SysCmd buses are bidirectional and driven by the processor or an external agent. Depending
on the direction, they are placed in either of the following two statuses.
Master status : The bus is driven by the processor, because a processor request is issued.
Slave status
: The bus is driven by an external agent, because an external request is issued.
The processor’s input/output timings are as follows:
The processor output starts to change at the rising edge of SClock.
The processor input is latched at the trailing edge of SClock.
Depending on the information included in the SysAD bus, two cycles occur as follows.
Address cycle : The SysAD bus contains a valid address.
Data cycle
: The SysAD bus contains valid data.
The interface control signals are briefly described below.
EValid
: Activate this signal when an external agent is in the master status and the SysAD and SysCmd
buses are valid.
: This signal is activated when the processor is in the master status and the SysAD and SysCmd
buses are valid.
: Activate this signal when an external agent requests the right to use the interface.
: This signal is activated when the processor requests the right to use the interface.
PMaster : This signal is activated when the processor is placed in the master status.
ERdy
: Activate this signal when an external agent becomes capable of accepting the processor
request.
PValid
EReq
PReq
4.1.1 System interface requests
The following requests are supported by the system interface.
Request
Outline
Data Unit
Processor read request
Read request to main memory or I/O
1 to 4 bytes (single);
Processor write request
Write request to main memory or I/O
2/4 words (block)
External write request
Interrupt request from the system bus
1 word
As an example of the system interface request protocol, Figure 4-1. shows the timing between a processor block
read request and the response.
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