參數(shù)資料
型號: μPD30100
廠商: NEC Corp.
英文描述: 64-bit RISC Microprosessor(64位 RISC 微處理器)
中文描述: 64位RISC Microprosessor(64位的RISC微處理器)
文件頁數(shù): 42/52頁
文件大小: 365K
代理商: ΜPD30100
42
μ
PD30100
Capacitance (T
A
= 25
°
C, V
DD
= 0 V)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Input capacitance
C
I
f
C
= 1 MHz
10
pF
Input/Output capacitance
C
IO
Pins other than tested pin: 0 V
10
pF
AC Characteristics (T
A
= –10 to +70
°
C, V
DD
= 2.2 to 3.6 V)
All the output timing is tested by the load capacity 40 pF.
(1) When 2.2
V
DD
< 2.7 V
Master clock and clock parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Master clock high-level width
t
KKH
115
ns
Master clock low-level width
t
KKL
115
ns
Master clock frequency
Note
1.5
4
MHz
Master clock cycle
t
CYK
250
666
ns
Clock jitter
t
Jitter
±
0.5
ns
Master clock rise time
t
KR
10
ns
Master clock fall time
t
KF
10
ns
Note
The operation of the V
R
4100 is guaranteed only when the PLL is enable.
The frequency of the master clock is 0 MHz when the PLL is in the self-running mode.
To set the processor in the self-running mode, fix the master clock to the high or low level.
Remark
The output of MasterOut is 500 kHz (TYP.) in the self-running mode.
System Interface Parameter
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Data output delay time
Note 1
t
DO
3
20
ns
Data setup delay time
Note 1
t
DS
5
ns
Data hold delay time
Note 1
t
DH
1
Note 2
ns
MasterOut rise time
t
MOR
7
ns
MasterOut fall time
t
MOF
7
ns
MasterOut high-level width
t
MOH
118
ns
MasterOut low-level width
t
MOL
118
ns
TClock rise time
t
TCR
5
ns
TClock fall time
t
TCF
5
ns
TClock high-level width
t
TCH
26
ns
TClock low-level width
t
TCL
26
ns
Notes 1.
Applied to all system interface pins
2.
Target value
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