TABLE
參數(shù)資料
型號： XRT86VL30IV-F
廠商： Exar Corporation
文件頁數(shù)： 6/175頁
文件大?。?/td> 0K
描述： IC FRAMR/LIU T1/E1/J1 QD 128LQFP
標準包裝： 72
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-LQFP（14x20）
包裝： 托盤
其它名稱： 1016-1485
XRT86VL30IV-F-ND
XRT86VL30
98
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 89: TRANSMIT SLIP COUNTER (TSC)
HEX ADDRESS: 0X090F
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
TxSLIP[7]
RUR
0
Performance Monitor - Transmit Slip Counter (8-bit Counter)
These Reset-Upon-Read bit fields reflect the cumulative number of
instances that Transmit Slip events have been detected by the T1
Framer since the last read of this register.
NOTE: A slip event is defined as a replication or deletion of a T1
frame by the transmit slip buffer.
6
TxSLIP[6]
RUR
0
5
TxSLIP[5]
RUR
0
4
TxSLIP[4]
RUR
0
3
TxSLIP[3]
RUR
0
2
TxSLIP[2]
RUR
0
1
TxSLIP[1]
RUR
0
TxSLIP[0]
RUR
0
TABLE 90: EXCESSIVE ZERO VIOLATION COUNTER MSB (EZVCU)
HEX ADDRESS: 0X0910
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
EZVC[15]
RUR
0
Performance Monitor - T1 Excessive Zero Violation 16-Bit
Counter - Upper Byte:
These RESET-upon-READ bits, along with that within the “PMON
T1 Excessive Zero Violation Counter Register LSB” combine to
reflect the cumulative number of instances that the ReceiveT1
Excessive Zero Violation has been detected by the Receive T1
Framer block since the last read of this register.
This register contains the Most Significant byte of this 16-bit of the
Receive T1 Excessive Zero Violation counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter first before reading the LSB counter in order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
6
EZVC[14]
RUR
0
5
EZVC[13]
RUR
0
4
EZVC[12]
RUR
0
3
EZVC[11]
RUR
0
2
EZVC[10]
RUR
0
1
EZVC[9]
RUR
0
EZVC[8]
RUR
0
TABLE 91: EXCESSIVE ZERO VIOLATION COUNTER LSB (EZVCL)
HEX ADDRESS: 0X0911
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
EZVC[7]
RUR
0
Performance Monitor - T1 Excessive Zero Violation 16-Bit
Counter - Lower Byte:
These RESET-upon-READ bits, along with that within the “PMON
T1 Excessive Zero Violation Counter Register MSB” combine to
reflect the cumulative number of instances that the ReceiveT1
Excessive Zero Violation has been detected by the Receive T1
Framer block since the last read of this register.
This register contains the Least Significant byte of this 16-bit of the
Receive T1 Excessive Zero Violation counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter first before reading the LSB counter in order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
6
EZVC[6]
RUR
0
5
EZVC[5]
RUR
0
4
EZVC[4]
RUR
0
3
EZVC[3]
RUR
0
2
EZVC[2]
RUR
0
1
EZVC[1]
RUR
0
EZVC[0]
RUR
0
相關(guān)PDF資料
PDF描述
XRT86VL32IB-F IC LIU/FRAMER T1/E1/J1 2CH 225BG
XRT86VL34IB-F IC LIU/FRAMER T1/E1/J1 4CH 225BG
XRT86VL38IB484-F IC LIU/FRAMER T1/E1/J1 8CH 484BG
XRT86VX38IB329-F IC TI/E1/J1 FRAMER/LIU 329FPBGA
XRT94L31IB-L IC MAPPER DS3/E3/STS-1 504TBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VL30IV-F 制造商:Exar Corporation 功能描述:T1/E1 Framer Combo IC
XRT86VL32 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL32_07 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
XRT86VL32_0709 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VL32_1 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*