TABLE
參數(shù)資料
型號： XRT86VL30IV-F
廠商： Exar Corporation
文件頁數(shù)： 104/175頁
文件大小： 0K
描述： IC FRAMR/LIU T1/E1/J1 QD 128LQFP
標(biāo)準包裝： 72
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-LQFP（14x20）
包裝： 托盤
其它名稱： 1016-1485
XRT86VL30IV-F-ND
XRT86VL30
29
SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. 1.0.1
TABLE 16: RECEIVE IN FRAME REGISTER (RIFR)
HEX ADDRESS: 0X0112
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
In Frame
RO
0
In Frame State
This READ-ONLY bit indicates whether the Receive T1 Framer block is
currently declaring the “In-Frame” condition with the incoming T1 data-
stream.
0 - Indicates that the Receive T1 Framer block is currently declaring the
LOF (Loss of Frame) Defect condition.
1 - Indicates that the Receive T1 Framer block is currently declaring itself
to be in the “In-Frame” condition.
6-0
Reserved
-
Reserved (E1 Mode Only)
TABLE 17: DATA LINK CONTROL REGISTER (DLCR1)
HEX ADDRESS: 0X0113
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
SLC-96 Data Link
Enable
R/W
0
SLC96 DataLink Enable
This bit permits the user to configure the channel to support the
transmission and reception of the “SLC-96 type” of data-link mes-
sage.
0 - Channel does not support the transmission and reception of
“SLC-96” type of data-link messages. Regular SF framing bits will
be transmitted.
1 - Channel supports the transmission and reception of the “SLC-
96” type of data-link messages.
This bit is only active if the channel has been configured to operate
in either the SLC-96 or the ESF Framing formats.
6
MOS ABORT Disable
R/W
0
MOS ABORT Disable:
This bit permits the user to either enable or disable the “Automatic
MOS ABORT” feature within Transmit HDLC Controller # 1. If the
user enables this feature, then Transmit HDLC Controller block # 1
will automatically transmit the ABORT Sequence (e.g., a zero fol-
lowed by a string of 7 consecutive “1s”) whenever it abruptly transi-
tions from transmitting a MOS type of message, to transmitting a
BOS type of message.
If the user disables this feature, then the Transmit HDLC Controller
Block # 1 will NOT transmit the ABORT sequence, whenever it
abruptly transitions from transmitting a MOS-type of message to
transmitting a BOS-type of message.
0 - Enables the “Automatic MOS Abort” feature
1 - Disables the “Automatic MOS Abort” feature
5
Rx_FCS_DIS
R/W
0
Receive Frame Check Sequence (FCS) Verification Enable/Dis-
able
This bit permits the user to configure the Receive HDLC Controller
Block # 1 to compute and verify the FCS value within each incoming
LAPD message frame.
0 - Enables FCS Verification
1 - Disables FCS Verification
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