TABLE
參數(shù)資料
型號(hào)： XRT86VL30IV-F
廠商： Exar Corporation
文件頁數(shù)： 109/175頁
文件大?。?/td> 0K
描述： IC FRAMR/LIU T1/E1/J1 QD 128LQFP
標(biāo)準(zhǔn)包裝： 72
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-LQFP（14x20）
包裝： 托盤
其它名稱： 1016-1485
XRT86VL30IV-F-ND
XRT86VL30
34
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 20: SLIP BUFFER CONTROL REGISTER (SBCR)
HEX ADDRESS: 0X0116
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
TxSB_ISFIFO
R/W
0
Transmit Slip Buffer Mode
This bit permits the user to configure the Transmit Slip Buffer to function as
either “Slip-Buffer” Mode, or as a “FIFO”, as depicted below.
0 - Configures the Transmit Slip Buffer to function as a “Slip-Buffer”.
1 - Configures the Transmit Slip Buffer to function as a “FIFO”.
NOTE: Transmit slip buffer is only used in high-speed or multiplexed mode
where TxSERCLKn must be configured as inputs only. Users must
make sure that the “Transmit Direction” timing (i.e. TxMSYNC) and
the TxSerClk input clock signal are synchronous to prevent any
transmit slips from occuring.
NOTE: The data latency is dictated by FIFO Latency in the FIFO Latency
Register (register 0x0117).
6-5
Reserved
-
Reserved
4
SB_FORCESF
R/W
0
Force Signaling Freeze
This bit permits the user to freeze any signaling update on the RxSIGn output
pin as well as the Receive Signaling Array Register -RSAR (0x0500-0x051F)
until this bit is cleared.
0 = Signaling on RxSIG and RSAR is updated immediately.
1 = Signaling on RxSIG and RSAR is not updated until this bit is set to ‘0’.
3
SB_SFENB
R/W
0
Signal Freeze Enable Upon Buffer Slips
This bit enables signaling freeze for one multiframe after the receive buffer
slips.
If signaling freeze is enabled, then the “Receive Channel” will freeze all sig-
naling updates on RxSIG pin and RSAR (0x0500-0x051F) for at least “one-
multiframe” period, after a “slip-event” has been detected within the “Receive
Slip Buffer”.
0 = Disables signaling freeze for one multi-frame after receive buffer slips.
1 = Enables signaling freeze for one multi-frame after receive buffer slips.
2
SB_SDIR
R/W
1
Slip Buffer (RxSync) Direction Select
This bit permits user to select the direction of the receive frame boundary
(RxSYNC) signal if the receive buffer is enabled. (i.e. SB_ENB[1:0] = 01 or
10). If slip buffer is bypassed, RxSYNC is always an output pin.
0 = Selects the RxSync signal as an output
1 = Selects the RxSync signal as an input
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VL30IV-F 制造商:Exar Corporation 功能描述:T1/E1 Framer Combo IC
XRT86VL32 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL32_07 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
XRT86VL32_0709 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VL32_1 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
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