參數(shù)資料
型號(hào)： XCF128XFTG64C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 65/88頁(yè)
文件大?。?/td> 0K
描述： IC PROM SRL 128M GATE 64-FTBGA
標(biāo)準(zhǔn)包裝： 1
可編程類型： 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量： 128Mb
電源電壓： 1.7 V ~ 2 V
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TBGA
供應(yīng)商設(shè)備封裝： 64-TFBGA
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 601 (CN2011-ZH PDF)
其它名稱： 122-1578
Platform Flash XL High-Density Configuration and Storage Device
DS617 (v3.0.1) January 07, 2010
Product Specification
68
R
Table 45: Bank and Erase Block Region 2 Information(1,2)
Offset
Data
Description
(P+32)h = 13Ch
01h
Number of identical banks within Bank Region 2
(P+33)h = 13Dh
00h
(P+34)h = 13Eh
11h
Number of program or erase operations allowed in Bank Region 2:
Bits 0–3: Number of simultaneous program operations
Bits 4–7: Number of simultaneous erase operations
(P+35)h = 13Fh
00h
Number of program or erase operations allowed in other banks while a bank in this region is
programming
Bits 0–3: Number of simultaneous program operations
Bits 4–7: Number of simultaneous erase operations
(P+36)h = 140h
00h
Number of program or erase operations allowed in other banks while a bank in this region is
erasing
Bits 0–3: Number of simultaneous program operations
Bits 4–7: Number of simultaneous erase operations
(P+37)h = 141h
02h
Types of erase block regions in Bank Region 2 n = number of erase block regions with
contiguous same-sized erase blocks. Symmetrically blocked banks have one blocking
region.(2)
(P+38)h = 142h
06h
Bank Region 2 Erase Block Type 1 Information
Bits 0–15: n+1 = number of identical-sized erase blocks
Bits 16–31: n×256 = number of bytes in erase block region
(P+39)h = 143h
00h
(P+3A)h = 144h
00h
(P+3B)h = 145h
02h
(P+3C)h = 146h
64h
Bank Region 2 (Erase Block Type 1)
Minimum block erase cycles × 1000
(P+3D)h = 147h
00h
(P+3E)h = 148h
01h
Bank Region 2 (Erase Block Type 1): Bits per cell, internal ECC
Bits 0–3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5–7: reserved
(P+3F)h = 149h
03h
Bank Region 2 (Erase Block Type 1):Page mode and Synchronous mode capabilities (defined
in Table 42, page 68)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3–7: reserved
(P+40)h = 14Ah
03h
Bank Region 2 Erase Block Type 2 Information
Bits 0–15: n+1 = number of identical-sized erase blocks
Bits 16–31: n×256 = number of bytes in erase block region
(P+41)h = 14Bh
00h
(P+42)h = 14Ch
80h
(P+43)h = 14Dh
00h
(P+44)h = 14Eh
64h
Bank Region 2 (Erase Block Type 2)
Minimum block erase cycles × 1000
(P+45)h = 14Fh
00h
(P+46)h = 150h
01h
Bank Region 2 (Erase Block Type 2): Bits per cell, internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5–7: reserved
(P+47)h = 151h
03h
Bank Region 2 (Erase Block Type 2): Page mode and Synchronous mode capabilities (defined
in Table 42, page 68)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3–7: reserved
(P+48)h = 152h
–
Feature Space definitions
(P+49)h = 153h
–
Reserved
Notes:
1.
The variable P is a pointer which is defined at CFI offset 015h.
2.
Bank Regions. There are two Bank Regions, see Table 35, page 61.
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