參數(shù)資料
型號: XCF128XFTG64C
廠商: Xilinx Inc
文件頁數(shù): 35/88頁
文件大?。?/td> 0K
描述: IC PROM SRL 128M GATE 64-FTBGA
標準包裝: 1
可編程類型: 系統(tǒng)內(nèi)可編程
存儲容量: 128Mb
電源電壓: 1.7 V ~ 2 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TBGA
供應商設備封裝: 64-TFBGA
包裝: 托盤
產(chǎn)品目錄頁面: 601 (CN2011-ZH PDF)
其它名稱: 122-1578
Platform Flash XL High-Density Configuration and Storage Device
DS617 (v3.0.1) January 07, 2010
Product Specification
40
R
X-Ref Target - Figure 20
Notes:
1.
Only on power-on-reset, FALS is initiated by READY_WAIT rising (Low-to-High) edge or G falling (High-to-Low) edge, whichever occurs last.
After POR, FALS is initiated only by a READY_WAIT rising edge.
Figure 20: First Address Latching Sequence (FALS)
Clock is not Free Running and G Transitions High-to-Low after READY_WAIT Goes High
Table 19: FALS Sequence Timings When the Clock Is Not Free Running
Symbol
Parameter
Voltage Range
Unit
VDDQ =
2.3V to 2.7V
VDDQ =
3.0V to 3.6V
TAVKH3
Address setup on third positive edge of clock
Min
9
ns
TKH3AX
Address hold on third positive edge of clock
Min
9
ns
TRWHKL
Clock Low after READY_WAIT High
Min
600
ns
TRWHKH
Clock High after READY_WAIT High
Min
600
ns
TGLKL
Clock Low after G Low
Min
600
ns
TGLKH
Clock High after G Low
Min
600
ns
K
G
L
A22–A0
First Address
FFFFh (Sync + Dummy Cycle)
DQ15–DQ0
READY_WAIT
First Address Latching Sequence
DS617_52_102308
RP
High
E
Low
T
GLKH
T
GLKL
T
KH3AX
T
AVKH3
V
DD/VDDQ
23
4
1
Address not Valid
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