參數(shù)資料
型號(hào)： XCF128XFTG64C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 27/88頁(yè)
文件大小： 0K
描述： IC PROM SRL 128M GATE 64-FTBGA
標(biāo)準(zhǔn)包裝： 1
可編程類型： 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量： 128Mb
電源電壓： 1.7 V ~ 2 V
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TBGA
供應(yīng)商設(shè)備封裝： 64-TFBGA
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 601 (CN2011-ZH PDF)
其它名稱： 122-1578
Platform Flash XL High-Density Configuration and Storage Device
DS617 (v3.0.1) January 07, 2010
Product Specification
33
R
The Clock signal is then halted at VIH or at VIL, and Output
Enable (G) goes High. When Output Enable goes Low
again and the Clock signal restarts, the Synchronous Burst
Read operation is resumed at its previous location.
When READY_WAIT (with CR4 = ‘0’) is gated by E, it
reverts to high impedance when G goes High.
See Table 29, page 52, and Figure 30, page 54 for details.
Single Synchronous Read Mode
Single Synchronous Read operations are similar to
Synchronous Burst Read operations except that the
memory outputs the same data to the end of the operation.
Synchronous Single Reads are used to read the Electronic
Signature, Status Register, CFI, Block Protection Status,
Configuration Register Status, or Protection Register. When
the addressed bank is in Read CFI, Read Status Register,
or Read Electronic Signature mode, the READY_WAIT
signal (if configured for the Wait function with CR4 = ‘0’) is
asserted during X-latency, the WAIT state and at the end of
a 4, 8 and 16-word burst. The signal is only deasserted
when output data is valid. See Table 29, page 52 and
Figure 27, page 51, for details.
Dual Operations and Multiple Bank Architecture
The Multiple Bank Architecture of Platform Flash XL gives
greater flexibility for software developers to split the code
and data spaces within the memory array. The Dual
Operations feature simplifies the software management of
the device by allowing code to be executed from one bank
while another bank is being programmed or erased. This
feature allows read operations with zero latency in one bank
while programming or erasing in another bank.
Note: Only one bank at a time is allowed to be in program or
erase mode.
If a read operation is required in a bank which is
programming or erasing, the program or erase operation
can be suspended. Also if the suspended operation is
erase, then a program command can be issued to another
block so that the device can have one block in Erase
Suspend mode, one in programming mode, and other
banks in read mode.
Bus Read operations are allowed in other banks between
setup and confirm cycles of program or erase operations.
By using a combination of these features, read operations
are always possible in Platform Flash XL.
Table 15 and Table 16, page 35 show which dual operations
are possible in other banks and in the same bank.
Dual operations between the Parameter Bank and either of
the CFI, OTP, or Electronic Signature memory spaces are
not allowed. Table 17, page 36 shows which dual
operations are allowed or not between the CFI, OTP,
Electronic Signature locations and the memory array.
Table 15: Dual Operations Allowed in Another Bank
Status of Bank
Commands Allowed in Another Bank
Read
Array
Read
Status
Register
Read CFI
Query
Read
Electronic
Signature
Program,
Buffer
Program
Block
Erase
Program/
Erase
Suspend
Program/
Erase Resume
Idle
Programming
––
–
Erasing
––
–
Program Suspended
––
–
Erase Suspended
––
Table 16: Dual Operations Allowed in Same Bank
Status of Bank
Commands Allowed in Same Bank
Read
Array
Read
Status
Register
Read CFI
Query
Read
Electronic
Signature
Program,
Buffer
Program
Block
Erase
Program/
Erase
Suspend
Program/
Erase Resume
Idle
Programming
–(1)
––
–
Erasing
–(1)
––
–
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