![](http://datasheet.mmic.net.cn/190000/UPD703111GM-10-UEU_datasheet_14990899/UPD703111GM-10-UEU_102.png)
CHAPTER 3 CPU FUNCTION
102
Preliminary User’s Manual U16031EJ2V1UD
(18/26)
Bit Units for Manipulation
Address
Function Register Name
Symbol
R/W
1 Bit
8 Bits 16 Bits
After Reset
FFFFFF22H
UF0 configuration/interface/
endpoint descriptor register 63
UF0CIE63
R/W
√
Undefined
FFFFFF23H
UF0 configuration/interface/
endpoint descriptor register 64
UF0CIE64
R/W
√
Undefined
FFFFFF24H
UF0 configuration/interface/
endpoint descriptor register 65
UF0CIE65
R/W
√
Undefined
FFFFFF25H
UF0 configuration/interface/
endpoint descriptor register 66
UF0CIE66
R/W
√
Undefined
FFFFFF26H
UF0 configuration/interface/
endpoint descriptor register 67
UF0CIE67
R/W
√
Undefined
FFFFFF27H
UF0 configuration/interface/
endpoint descriptor register 68
UF0CIE68
R/W
√
Undefined
FFFFFF28H
UF0 configuration/interface/
endpoint descriptor register 69
UF0CIE69
R/W
√
Undefined
FFFFFF29H
UF0 configuration/interface/
endpoint descriptor register 70
UF0CIE70
R/W
√
Undefined
FFFFFF2AH
UF0 configuration/interface/
endpoint descriptor register 71
UF0CIE71
R/W
√
Undefined
FFFFFF2BH
UF0 configuration/interface/
endpoint descriptor register 72
UF0CIE72
R/W
√
Undefined
FFFFFF2CH
UF0 configuration/interface/
endpoint descriptor register 73
UF0CIE73
R/W
√
Undefined
FFFFFF2DH
UF0 configuration/interface/
endpoint descriptor register 74
UF0CIE74
R/W
√
Undefined
FFFFFF2EH
UF0 configuration/interface/
endpoint descriptor register 75
UF0CIE75
R/W
√
Undefined
FFFFFF2FH
UF0 configuration/interface/
endpoint descriptor register 76
UF0CIE76
R/W
√
Undefined
FFFFFF30H
UF0 configuration/interface/
endpoint descriptor register 77
UF0CIE77
R/W
√
Undefined
FFFFFF31H
UF0 configuration/interface/
endpoint descriptor register 78
UF0CIE78
R/W
√
Undefined
FFFFFF32H
UF0 configuration/interface/
endpoint descriptor register 79
UF0CIE79
R/W
√
Undefined
FFFFFF33H
UF0 configuration/interface/
endpoint descriptor register 80
UF0CIE80
R/W
√
Undefined
FFFFFF34H
UF0 configuration/interface/
endpoint descriptor register 81
UF0CIE81
R/W
√
Undefined
FFFFFF35H
UF0 configuration/interface/
endpoint descriptor register 82
UF0CIE82
R/W
√
Undefined
FFFFFF36H
UF0 configuration/interface/
endpoint descriptor register 83
UF0CIE83
R/W
√
Undefined
FFFFFF37H
UF0 configuration/interface/
endpoint descriptor register 84
UF0CIE84
R/W
√
Undefined