
CHAPTER 3 CPU FUNCTION
98
Preliminary User’s Manual U16031EJ2V1UD
(14/26)
Bit Units for Manipulation
Address
Function Register Name
Symbol
R/W
1 Bit
8 Bits 16 Bits
After Reset
FFFFFE83H
UF0 EP0 write register
UF0E0W
W
√
Undefined
FFFFFE84H
UF0 bulk out 1 register
UF0BO1
R
√
Undefined
FFFFFE85H
UF0 bulk out 1 length register
UF0BO1L
R
√
00H
FFFFFE86H
UF0 bulk out 2 register
UF0BO2
R
√
Undefined
FFFFFE87H
UF0 bulk out 2 length register
UF0BO2L
R
√
00H
FFFFFE88H
UF0 bulk in 1 register
UF0BI1
W
√
Undefined
FFFFFE89H
UF0 bulk in 2 register
UF0BI2
W
√
Undefined
FFFFFE8AH
UF0 interrupt 1 register
UF0INT1
W
√
Undefined
FFFFFE8BH
UF0 interrupt 2 register
UF0INT2
W
√
Undefined
FFFFFEA2H
UF0 device status register L
UF0DSTL
R/W
√
00H
FFFFFEA6H
UF0 EP0 status register L
UF0E0SL
R/W
√
00H
FFFFFEA8H
UF0 EP1 status register L
UF0E1SL
R/W
√
00H
FFFFFEAAH
UF0 EP2 status register L
UF0E2SL
R/W
√
00H
FFFFFEACH
UF0 EP3 status register L
UF0E3SL
R/W
√
00H
FFFFFEAEH
UF0 EP4 status register L
UF0E4SL
R/W
√
00H
FFFFFEB4H
UF0 EP7 status register L
UF0E7SL
R/W
√
00H
FFFFFEB6H
UF0 EP8 status register L
UF0E8SL
R/W
√
00H
FFFFFEC0H
UF0 address register
UF0ADRS
R
√
00H
FFFFFEC1H
UF0 configuration register
UF0CNF
R
√
00H
FFFFFEC2H
UF0 interface 0 register
UF0IF0
R
√
00H
FFFFFEC3H
UF0 interface 1 register
UF0IF1
R
√
00H
FFFFFEC4H
UF0 interface 2 register
UF0IF2
R
√
00H
FFFFFEC5H
UF0 interface 3 register
UF0IF3
R
√
00H
FFFFFEC6H
UF0 interface 4 register
UF0IF4
R
√
00H
FFFFFED0H
UF0 descriptor length register
UF0DSCL
R/W
√
00H
FFFFFED1H
UF0 device descriptor register 0
UF0DD0
R/W
√
Undefined
FFFFFED2H
UF0 device descriptor register 1
UF0DD1
R/W
√
Undefined
FFFFFED3H
UF0 device descriptor register 2
UF0DD2
R/W
√
Undefined
FFFFFED4H
UF0 device descriptor register 3
UF0DD3
R/W
√
Undefined
FFFFFED5H
UF0 device descriptor register 4
UF0DD4
R/W
√
Undefined
FFFFFED6H
UF0 device descriptor register 5
UF0DD5
R/W
√
Undefined
FFFFFED7H
UF0 device descriptor register 6
UF0DD6
R/W
√
Undefined
FFFFFED8H
UF0 device descriptor register 7
UF0DD7
R/W
√
Undefined
FFFFFED9H
UF0 device descriptor register 8
UF0DD8
R/W
√
Undefined
FFFFFEDAH
UF0 device descriptor register 9
UF0DD9
R/W
√
Undefined
FFFFFEDBH
UF0 device descriptor register 10
UF0DD10
R/W
√
Undefined
FFFFFEDCH
UF0 device descriptor register 11
UF0DD11
R/W
√
Undefined
FFFFFEDDH
UF0 device descriptor register 12
UF0DD12
R/W
√
Undefined