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| 型號(hào)： | UPD703111GM-10-UEU |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, FINE PITCH, PLASTIC, LQFP-176 |
| 文件頁(yè)數(shù)： | 146/238頁(yè) |
| 文件大?。?/td> | 6598K |
| 代理商： | UPD703111GM-10-UEU |
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Preliminary User’s Manual U16031EJ2V1UD
23
LIST OF FIGURES (4/6)
Figure No.
Title
Page
10-12
Example of Continuous Reception Processing Flow in Single Mode (CPU Control) ..................................523
10-13
Example of Continuous Transmission Processing Flow in Single Mode (DMA Control).............................524
10-14
Example of Continuous Reception Processing Flow in Single Mode (DMA Control)..................................525
10-15
Example of Continuous Transmission Processing Flow in FIFO Mode (CPU Control) ...............................526
10-16
Example of Continuous Reception Processing in FIFO Mode (CPU Control).............................................527
10-17
Example of Continuous Transmission (Pending Mode) Processing in FIFO Mode (DMA Control).............528
10-18
Example of Continuous Reception (Pending Mode) Processing Flow in FIFO Mode (DMA Control) .........529
10-19
Example of Reception Error Processing in Single Mode ............................................................................530
10-20
Example of Reception Error Processing Flow in FIFO Mode (1) ................................................................531
10-21
Example of Reception Error Processing Flow in FIFO Mode (2) ................................................................532
10-22
Block Diagram of Clocked Serial Interfaces 30 and 31...............................................................................535
10-23
Transfer Clock of CSI3n .............................................................................................................................548
10-24
Function of CSI Data Buffer Register n (CSIBUFn) ....................................................................................551
10-25
Transfer Data Length: 8 Bits (CCLn3 to CCLn0 Bits = 1000 in CSIL3n Register),
Transfer Direction: MSB First (DIRn Bit = 0 in CSIM3n Register)...............................................................552
10-26
Transfer Data Length: 8 Bits (CCLn3 to CCLn0 Bits = 1000 in CSIL3n Register),
Transfer Direction: LSB First (DIRn Bit = 1 in CSIM3n Register)................................................................554
10-27
Transfer Data Length: 16 Bits (CCLn3 to CCLn0 Bits = 0000 in CSIL3n Register),
Transfer Direction: MSB First (DIRn Bit = 0 in CSIM3n Register)...............................................................556
10-28
Clock Timing...............................................................................................................................................557
10-29
Master Mode (CKPn and DAPn Bits = 00 in CSIC3n Register,
CCLn3 to CCLn0 Bits = 1000 in CSIL3n Register (Transfer Data Length: 8 Bits)) .....................................558
10-30
Slave Mode (CKPn and DAPn Bits = 00 in CSIC3n Register,
CCLn3 to CCLn0 Bits = 1000 in CSIL3n Register (Transfer Data Length: 8 Bits)) .....................................559
10-31
Single Mode................................................................................................................................................561
10-32
Continuous Mode .......................................................................................................................................563
10-33
Delay Control of Transmission/Reception Completion Interrupt (INTCSI3n):
CSITn Bit = 1 in CSIC3n Register, CSWEn Bit = 0, CKPn and DAPn Bits = 00,
CCLn3 to CCLn0 Bits = 1000 in CSIL3n Register (Transfer Data Length: 8 Bits) ......................................565
10-34
Enabling/Disabling Transfer Wait ...............................................................................................................566
11-1
Operation of UF0E0R Register...................................................................................................................640
11-2
Operation of UF0E0ST Register.................................................................................................................642
11-3
Operation of UF0E0W Register ..................................................................................................................644
11-4
Operation of UF0BO1 Register...................................................................................................................646
11-5
Operation of UF0BO2 Register...................................................................................................................650
11-6
Operation of UF0BI1 Register ....................................................................................................................653
11-7
Operation of UF0BI2 Register ....................................................................................................................657
11-8
Operation of UF0INT1 Register ..................................................................................................................661
11-9
Operation of UF0INT2 Register ..................................................................................................................663
11-10
Initializing Request Data Register Area ......................................................................................................687
11-11
Initialization of Request Data Register Area ...............................................................................................688
11-12
Setting of Interface and Endpoint ...............................................................................................................688
11-13
Setting of Interrupt ......................................................................................................................................689
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