- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄297644 > UPD703111GM-10-UEU 32-BIT, 100 MHz, RISC MICROCONTROLLER, PQFP176 PDF資料下載
參數(shù)資料
| 型號(hào)： | UPD703111GM-10-UEU |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, FINE PITCH, PLASTIC, LQFP-176 |
| 文件頁(yè)數(shù)： | 168/238頁(yè) |
| 文件大?。?/td> | 6598K |
| 代理商： | UPD703111GM-10-UEU |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)當(dāng)前第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)
CHAPTER 1 INTRODUCTION
35
Preliminary User’s Manual U16031EJ2V1UD
1.6.2 On-chip units
(1) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic
logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits
× 16 bits → 32 bits or 32 bits × 32 bits → 64
bits) and a barrel shifter (32 bits), help accelerate processing of complex instructions.
(2) Bus control unit (BCU)
The BCU starts the required external bus cycle based on the physical address obtained by the CPU. When
an instruction is fetched from external memory area and the CPU does not send a bus cycle start request, the
BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is
stored in an instruction queue in the CPU.
The BCU controls a DRAM controller (DRAMC), page ROM controller (ROMC), and DMA controller (DMAC)
and performs external memory access and DMA transfer.
(a) SDRAM controller
The SDRAM controller generates the SDRAS, SDCAS, UUDQM, ULDQM, LUDQM, and LLDQM signals
and performs access control for SDRAM.
CAS latency 1 (excluding flyby DMA transfer), 2, and 3 are supported, and the burst length is fixed to 1.
A refresh function that supports the CBR refresh cycle and a dynamic self-refresh function based on an
external input are also available.
(b) Page ROM controller (ROMC)
This controller supports accessing ROM that includes the page access function.
It performs address comparisons with the immediately preceding bus cycle and executes wait control for
normal access (off-page)/page access (on-page). It can handle page widths of 8 to 128 bytes.
(c) DMA controller (DMAC)
This controller controls data transfer between memory and I/O instead of the CPU.
There are two address modes: flyby (1-cycle) transfer, and 2-cycle transfer. There are three bus modes,
single transfer, single step transfer, and block transfer.
(3) RAM
Instruction RAM (128 KB) and data RAM (16 KB) are provided.
The instruction RAM can be accessed in one clock from the CPU when an instruction is fetched. Its write
access time depends on the BUSCLK frequency to the CS0 space and the number of wait cycles. This RAM
is mapped from address 00000000H.
The data RAM can be accessed in one clock from the CPU when its data is read. It is mapped from address
FFFF8000H.
(4) Cache
An instruction cache (8 KB) is provided.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD703111GM-15-UEU | 32-BIT, 150 MHz, RISC MICROCONTROLLER, PQFP176 |
| UPD70F3271YGF-JBT-A | 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100 |
| UPD70F3261YGF-JBT-A | 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100 |
| UPD780031AYCW(A)-XXX | 8-BIT, MROM, 8.38 MHz, MICROCONTROLLER, PDIP64 |
| UPD780123GB(A1)-XXX-8ET | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP52 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD703114 | 制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers |
| UPD703114A | 制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers |
| UPD703114GCA-XXX-8EU | 制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers |
| UPD703114GCA-XXX-8EU-A | 制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers |
| UPD703114GC-XXX-8EU | 制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。