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| 型號： | UPD703111GM-10-UEU |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, FINE PITCH, PLASTIC, LQFP-176 |
| 文件頁數(shù)： | 135/238頁 |
| 文件大?。?/td> | 6598K |
| 代理商： | UPD703111GM-10-UEU |
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Preliminary User’s Manual U16031EJ2V1UD
22
LIST OF FIGURES (3/6)
Figure No.
Title
Page
9-5
TMC1 Capture Operation Example (When Both Edges Are Specified) ......................................................419
9-6
Compare Operation Example .....................................................................................................................420
9-7
TMC1 Compare Operation Example (Set/Reset Output Mode) ..................................................................422
9-8
Contents of Register Settings When Timer C Is Used as Interval Timer.....................................................423
9-9
Interval Timer Operation Timing Example...................................................................................................424
9-10
Contents of Register Settings When Timer C Is Used for PWM Output......................................................425
9-11
PWM Output Operation Timing Example ....................................................................................................426
9-12
Contents of Register Settings When Timer C Is Used for Cycle Measurement ..........................................428
9-13
Cycle Measurement Operation Timing Example.........................................................................................429
9-14
Timer D Block Diagram...............................................................................................................................431
9-15
Example of Timing During TMDn Operation ...............................................................................................434
9-16
TMD0 Compare Operation Example...........................................................................................................437
9-17
Timer ENC1 Block Diagram ........................................................................................................................443
9-18
TMENC1n Block Diagram (During PWM Output Operation).......................................................................462
9-19
PWM Signal Output Example (When ALVT1n0 Bit = 0 Is Set)....................................................................463
9-20
Mode 1 (When Rising Edge Is Specified as Valid Edge of TIUD1n Pin) .....................................................465
9-21
Mode 1 (When Rising Edge Is Specified as Valid Edge of TIUD1n Pin):
In Case of Simultaneous TIUD1n, TCUD1n Pin Edge Timing ....................................................................465
9-22
Mode 2 (When Rising Edge Is Specified as Valid Edge of TIUD1n, TCUD1n Pins) ...................................466
9-23
Mode 3 (When Rising Edge Is Specified as Valid Edge of TIUD1n pin) .....................................................467
9-24
Mode 3 (When Rising Edge Is Specified as Valid Edge of TIUD1n Pin):
In Case of Simultaneous TIUD1n, TCUD1n Pin Edge Timing ....................................................................467
9-25
Mode 4........................................................................................................................................................468
9-26
Example of TMENC1n Operation When Interval Operation and Transfer Operation Are Combined ..........469
9-27
Example of TMENC1n Operation in UDC Mode .........................................................................................471
9-28
Clear Operation upon Match with CM1n0 During TMENC1n Up Count Operation .....................................472
9-29
Clear Operation upon Match with CM1n1 During TMENC1n Down Count Operation.................................472
9-30
Count Value Clear Operation upon Compare Match...................................................................................473
9-31
Internal Operation During Transfer Operation.............................................................................................473
9-32
Interrupt Output upon Compare Match (CM1n1 with Operation
Mode Set to General-Purpose Timer Mode and Count Clock Set to fX/8)...................................................474
9-33
UBD1n Flag Operation................................................................................................................................474
10-1
Block Diagram of Asynchronous Serial Interfaces B0 and B1 ....................................................................481
10-2
Asynchronous Serial Interface Transmit/Receive Data Format (LSB-First Transfer) ..................................505
10-3
Timing of Asynchronous Serial Interface Transmission Completion Interrupt (UBTITn) .............................508
10-4
Timing of Asynchronous Serial Interface FIFO Transmission Completion Interrupt (UBTIFn) ....................508
10-5
Timing of Asynchronous Serial Interface Reception Completion Interrupt (UBTIRn) ..................................512
10-6
Noise Filter Circuit.......................................................................................................................................515
10-7
Timing of RXDn Signal Judged as Noise ....................................................................................................515
10-8
Baud Rate Generator Configuration............................................................................................................516
10-9
Allowable Baud Rate Range During Reception ..........................................................................................519
10-10
Transfer Rate During Continuous Transmission .........................................................................................521
10-11
Example of Continuous Transmission Processing Flow in Single Mode (CPU Control) .............................522
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