參數(shù)資料
型號: UPD30181AYF1-131-GA3
廠商: NEC Corp.
英文描述: 64-/32-BIT MICROPROCESSOR
中文描述: 64-/32-BIT微處理器
文件頁數(shù): 52/72頁
文件大?。?/td> 447K
代理商: UPD30181AYF1-131-GA3
Data Sheet U16277EJ1V0DS
52
μ
PD30181A, 30181AY
(d) External ISA bus space access (READY mode) timing (RDYSYN = 1)
Hi-Z
Hi-Z
Hi-Z
t
EXS
t
EXH
t
EXCL
t
EXRDYH
2t
TClock
+t
LClock
+t
EXD
t
EXCS16H
t
LClock
+t
EXD
t
TClock
+t
EXD
t
TClock
+t
EXD
Note
CSOFF
+t
EXD
CONOFF
+t
EXD
CONSET
+t
EXD
IOCS16SET
+t
EXD
BUSIDLE
+t
EXD
t
EXD
t
EXD
t
EXD
t
EXZ
t
EXD
A(24:0), UBE#
(output)
IORD#, IOWR#,
MEMRD#, MEMWR#
(output)
SYSDIR
(output)
IORDY
(input)
IOCS16#
(input)
SYSEN#
(output)
D(15:0)
(write)
D(15:0)
(read)
Note
RMINWID
+t
EXD
t
EXD
Input
Note
Output
Remarks 1.
IOCS16SET, CONSET, CSOFF, RMINWID, CONOFF, and BUSIDLE are the timing parameters
that can be changed by setting registers of the EXIBU. Each timing parameter is defined as the
number of LClock cycles.
2.
The circles indicate the sampling timing.
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