參數(shù)資料
型號： UPD30181AYF1-131-GA3
廠商： NEC Corp.
英文描述： 64-/32-BIT MICROPROCESSOR
中文描述： 64-/32-BIT微處理器
文件頁數(shù)： 33/72頁
文件大?。?/td> 447K
代理商： UPD30181AYF1-131-GA3
Data Sheet U16277EJ1V0DS
33
μ
PD30181A, 30181AY
1.3 Pin I/O Circuit Types and Recommended Connection of Unused Pins
(1/3)
Pin Name
I/O
I/O Circuit Type
Recommended Connection of Unused Pins
A24/CKE1
O
A
Leave open
A23/RP#
O
A
Leave open
A(22:15)/GPIO(61:54)
I/O
A
Leave open
A(14:0)
O
A
Leave open
SA10
O
A
Leave open
D(31:0)
I/O
A
Connect to VDD3 or GND3 via a resistor
IORD#
O
A
Leave open
IOWR#
O
A
Leave open
IORDY
I
A
Connect to VDD3
IOCS16#
I
A
Connect to VDD3
UBE#
O
A
Leave open
PCS(4:0)#
O
A
Leave open
SYSDIR
O
A
Leave open
SYSEN#
O
A
Leave open
DRQ(1:0)#
I
A
Connect to VDD3
DAK(1:0)#
O
A
Leave open
TC(1:0)#/GPIO(53:52)
I/O
A
Leave open
NMI#
I
A
Connect to VDD3
ROMCS#
O
A
Leave open
MEMRD#
O
A
Leave open
MEMWR#
O
A
Leave open
SDCLK
O
A
Leave open
CKE0
O
A
Leave open
SDCS(3:0)#
O
A
Leave open
RAS#
O
A
Leave open
CAS#
O
A
Leave open
DQM(3:0)/LBE(3:0)#
O
A
Leave open
WE#
O
A
Leave open
POWER
I
B
Connect to VDD3
RSTSW#
I
B
Connect to VDD3
RTCRST#
I
B
–
POWERON
O
A
Leave open
MPOWER
O
A
Leave open
DCLK/SHCLK
O
A
Leave open
HSYNC/LOCLK/NWIREEN
Note
I/O
A
Connect to VDD3 or GND3 via a resistor
VSYNC/FLM/BMODE1
Note
I/O
A
Connect to VDD3 or GND3 via a resistor
Note
The signal level is sampled when the RTCRST# signal has changed to high level.
相關(guān)PDF資料
PDF描述
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