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| 型號： | UPD30181AYF1-131-GA3-A |
| 廠商： | NEC Corp. |
| 英文描述： | 64-/32-BIT MICROPROCESSOR |
| 中文描述： | 64-/32-BIT微處理器 |
| 文件頁數(shù)： | 1/72頁 |
| 文件大?。?/td> | 447K |
| 代理商： | UPD30181AYF1-131-GA3-A |
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The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
MOS INTEGRATED CIRCUIT
μ
PD30181A, 30181AY
V
R
4181A
TM
64-/32-BIT MICROPROCESSOR
DATA SHEET
2002
1997
The mark
shows major revised points.
Document No. U16277EJ1V0DS00 (1st edition)
Date Published October 2002 N CP(K)
Printed in Japan
DESCRIPTION
The
μ
PD30181A and 30181AY (V
R
4181A), which are high-performance 64-/32-bit microprocessors employing the
RISC (reduced instruction set computer) architecture developed by MIPS
microprocessors manufactured by NEC.
The V
R
4181A includes as its CPU the V
R
4120 core, an ultra-low-power-consumption core featuring cache
memory, a high-speed product-sum operation unit, and a memory management unit. Other on-chip components
include an LCD controller, CompactFlash controller, USB host/function controller, DMA controller, SDRAM controller,
PWM controller, AC97/I
interface, keyboard interface, touch panel interface, real-time clock, A/D converter, D/A converter, and other
controllers and interfaces required for battery-driven mobile information devices, fixed compact information devices,
car navigation systems, and compact embedded devices.
TM
, are products in the V
R
Series
TM
of
2
S audio interface, full-duplex asynchronous serial interface, IrDA interface, I
2
C serial
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V
R
4181A Hardware User’s Manual (U16049E)
V
R
4100 Series
Architecture User’s Manual (U15509E)
FEATURES
{
V
R
4120 core (64-bit RISC core) on chip as CPU
{
Pipeline clock: 131 MHz
{
Conforms to MIPS III (except for FPU, LL and SC
instructions) and MIPS16 instruction sets
{
Supports MACC and DMACC high-speed product-sum
operation instructions
{
On-chip cache memory
Capacity includes 8 KB instruction cache and 8 KB
data cache
{
Employs a writeback cache
{
Physical addresses: 32 bits
Virtual addresses: 40 bits
{
On-chip 32 double-entry TLB
{
Effective power management using four modes:
Fullspeed, Standby, Suspend, and Hibernate
{
Employs a high-performance internal system bus (T-
bus)
{
DRAM controller supporting 64 Mb, 128 Mb, and 256
Mb SDRAMs
{
External system bus interface supporting ROM, page
ROM, flash memory, SRAM, ISA devices, IDE (ATA)
devices, and SyncFlash memory
{
UMA type LCD controller (supports STN and TFT
panels)
{
ExCA register-compatible CompactFlash interface (2
slots)
{
USB host controller (Rev1.1, OHCI Rev1.0)
controller
{
USB function (Rev1.1) controller
{
AC97 and I
{
Clocked serial interface (1 channel)
{
NS16550-compatible serial interface (3 channels)
{
IrDA (SIR) interface (1 channel)
{
I
{
PWM controller (3 channels)
{
DMA controller supporting chain mode (4 channels)
{
Keyboard scan interface (supports 8 × 12 key matrix)
{
X-Y coordinate auto scan touch panel interface
{
On-chip A/D converter and D/A converter
{
On-chip watchdog timer unit
{
RTC unit (total of 3 timer and counter channels)
{
On-chip PLL and clock generators
{
Power supplies: 2.5 V for core, 3.3 V for I/O block
{
Package: 240-pin plastic FBGA
2
S audio interfaces (1 channel each)
C bus interfaces (2 channels,
μ
PD30181AY only)
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