參數(shù)資料
型號： UPD30181AYF1-131-GA3-A
廠商： NEC Corp.
英文描述： 64-/32-BIT MICROPROCESSOR
中文描述： 64-/32-BIT微處理器
文件頁數(shù)： 24/72頁
文件大?。?/td> 447K
代理商： UPD30181AYF1-131-GA3-A
Data Sheet U16277EJ1V0DS
24
μ
PD30181A, 30181AY
(18) Mode setting signals
These signals are used to set various modes.
These signals are sampled only when the RTCRST# signal has changed to high level. At all other times, they
can be used as alternate-function pins.
In order to disconnect a pull-up or pull-down resistor for mode setting during normal operation, use a switch
linked to the RTCRST# signal.
Signal Name
I/O
Function
Alternate Function
BMODE1
I
VSYNC, FLM
BMODE0
I
Boot ROM type setting
BMODE(1:0) = 01: ROM/flash memory
BMODE(1:0) = 10: SyncFlash memory
BMODE(1:0) = 00 or 11: Setting prohibited
ENAB, M
NWIREEN
I
N-Wire use enable signal
0: Disabled
1: Enabled
HSYNC, LOCLK
DBUS32
I
Boot ROM bus width specification
0: 16 bits
1: 32 bits
CF1_RESET
CLKSEL2
I
TxD0
CLKSEL1
I
RTS0#, GPIO19
CLKSEL0
I
Set frequency of CPU core’s pipeline reference clock (AClock)
CLKSEL(2:0) = 111: Setting prohibited (147.4 MHz)
CLKSEL(2:0) = 110: 131.1 MHz
CLKSEL(2:0) = 101: 118.0 MHz
CLKSEL(2:0) = 100: 98.3 MHz
CLKSEL(2:0) = 011: 90.7 MHz
CLKSEL(2:0) = 010: 84.1 MHz
CLKSEL(2:0) = 001: 78.5 MHz
CLKSEL(2:0) = 000: 73.7 MHz
DTR0#, RTS1#,
GPIO17
DIVMODE1
I
RTS2#, SYNC,
WS
DIVMODE0
I
Set division ratio of AClock and internal system bus reference clock
(TClock)
DIVMODE(1:0) = 10: AClock/2 (DIV2 mode)
DIVMODE(1:0) = 01: AClock/3 (DIV3 mode)
DIVMODE(1:0) = 11, 00: Setting prohibited
DTR2#, SDO,
SDATAOUT
MIPS16EN
I
Enables use of MIPS16 instruction set
0: Use disabled
1: Use enabled
TxD2, IRDOUT
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