參數(shù)資料
型號(hào)： UPD30181AYF1-131-GA3-A
廠商： NEC Corp.
英文描述： 64-/32-BIT MICROPROCESSOR
中文描述： 64-/32-BIT微處理器
文件頁數(shù)： 38/72頁
文件大?。?/td> 447K
代理商： UPD30181AYF1-131-GA3-A
Data Sheet U16277EJ1V0DS
38
μ
PD30181A, 30181AY
DC Characteristics (T
A
= –40 to +85
°
C, V
DD25
= 2.3 to 2.7 V, V
DD33
= 3.0 to 3.6 V)
(1) Pins of I/O circuit types A, C, and D
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Output voltage, high
V
OH
Pins of types A
Note 1
, C
Note 2
, and D
Note 3
,
I
OH
=
2 mA
0.8V
DD33
V
Output voltage, low
V
OL
Pins of types A
Note 1
, C
Note 2
, and D
Note 3
,
I
OL
= 2 mA
0.4
V
V
IH
Pins of types A
Note 1
(excluding GPIO pin of
edge triggered interrupt), C
Note 2
, and D
Note 3
2.0
V
DD33
+ 0.3
V
Input voltage, high
V
IH1E
Pins of type A
Note 4
(GPIO pin of edge
triggered interrupt)
0.75V
DD33
V
DD33
+ 0.3
V
V
IL
Pins of type A
Note 1
(excluding GPIO pin of
edge triggered interrupt), C
Note 2
, and D
Note 3
0.3
0.25V
DD33
V
Input voltage, low
V
IL1E
Pins of type A
Note 4
(GPIO pin of edge
triggered interrupt)
0.3
0.5
V
Notes 1.
Applies to the following pins.
D(31:0), IORDY, IOCS16#, DRQ(1:0)#, TC(1:0)#/GPIO(53:52), NMI#, HSYNC/LOCLK/NWIREEN,
ENAB/M/BMODE0, VSYNC/FLM/BMODE1, FPD15/CF1_READY/GPIO51,
FPD14/CF1_STSCHG#/GPIO50, FPD(13:12)/CF1_CE(2:1)#/GPIO(49:48),
FPD(11:10)/CF1_CD(2:1)#/GPIO(47:46), FPD(9:4)/GPIO(45:40), CLK48, JTCK, JTMS, JTDI/RMODE#,
JTRST#, BKTGIO#, A(14:0), A23/RP#, A24/CKE1, CAS#, CKE0, DAK(1:0)#, DCLK/SHCLK, DQM(3:0),
FPD(3:0), IORD#, JTDO, MEMRD#, MEMWR#, MPOWER, PCS(4:0)#, POWERON, RAS#, ROMCS#,
SA10, SDCLK, SDCS(3:0)#, SYSDIR, SYSEN#, UBE#, UPON, VPBIAS/GPO63, VPLCD/GPO62, WE#
2.
Applies to the TPX(1:0) and TPY0 pins.
3.
Applies to the TPY1 pin.
4.
Applies to the following pins.
FPD(9:4)/GPIO(45:40), FPD(11:10)/CF1_CD(2:1)#/GPIO(47:46),
FPD(13:12)/CF1_CE(2:1)#/GPIO(49:48), FPD14/CF1_STSCHG#/GPIO50,
FPD15/CF1_READY/GPIO51, TC(1:0)#/GPIO(53:52), A(22:15)/GPIO(61:54)
Remark
For details of the I/O circuits, refer to
1.4 Pin I/O Circuits
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