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Data Sheet U16277EJ1V0DS
54
μ
PD30181A, 30181AY
(6) CompactFlash/PC Card/ATA (IDE) interface (ECU) parameters
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
TClock frequency
f
TClock
65.55
MHz
TClock cycle
t
TClock
15.26
ns
LClock frequency
f
LClock
32.78
MHz
LClock cycle
t
LClock
30.52
ns
ECU_SysClock frequency
f
ECU_SysClock
32.78
MHz
ECU_SysClock cycle
t
ECU_SysClock
30.52
ns
Output delay time (EXIBU)
t
EXD
0
12
ns
Output delay time (ECU)
t
ECUD
0
TBD
ns
Data input setup time
t
EXS
5
ns
Data input hold time
t
EXH
0
ns
Data output float delay time
t
EXZ
10
ns
Data output setup time
(to command signal
↓
)
t
EXCL
0
ns
CF_WAIT# input hold time
t
ECURDYH
0
ns
CF0_IOIS16# input hold time
t
ECUCS16H
0
ns
Remarks 1.
TClock is generated by dividing AClock in accordance with the setting of the DIVMODE(1:0) signals
when the RTCRST# signal changes to high level. After releasing the RTC reset, the division ratio of
TClock can be changed by setting the PMUDIVREG register.
2.
LClock is generated by dividing TClock in accordance with the setting of the LCLKDIV(1:0) bits of
the EXIBUCFG register in the EXIBU.
3.
ECU_SysClock is generated by dividing TClock in accordance with the setting of the
ECUSYSCLKDIV(1:0) bits of the CLKDIVCTRL register in the CCU.
4.
MEMRD#, MEMWR#, IORD#, and IOWR# signals are called as command signals for the external
system bus interface.
(a) Relationship between ECU bus cycle type and ECUWAIT
ECUWAIT Value (ns)
Bus Cycle
Number of Wait
Cycles
MIN.
MAX.
16-bit I/O cycle (IOnWT = 1)
2
t
ECU_SysClock
×
2
16-bit I/O cycle(IOnWT = 0)
3
t
ECU_SysClock
×
3
8-bit I/O cycle (Wn_IOWS = 1)
4
t
ECU_SysClock
×
4
8-bit I/O cycle (Wn_IOWS = 0)
5
t
ECU_SysClock
×
5
16-bit memory cycle
(ZWSEN = 1 and M16W(1:0) = 0)
0
16-bit memory cycle
(ZWSEN = 0 and M16W(1:0) = N)
N + 1
t
ECU_SysClock
×
(N + 1)
8-bit memory cycle (ZWSEN = 1)
0
0
8-bit memory cycle (ZWSEN = 0)
5
t
ECU_SysClock
×
4
Remarks 1.
IOnWT, Wn_IOWS, ZWSEN, and M16W(1:0) are bits of the register in the ECU.
2.
n = 0, 1