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參數(shù)資料
| 型號(hào)： | UPD30181AYF1-131-GA3-A |
| 廠商： | NEC Corp. |
| 英文描述： | 64-/32-BIT MICROPROCESSOR |
| 中文描述： | 64-/32-BIT微處理器 |
| 文件頁數(shù)： | 12/72頁 |
| 文件大?。?/td> | 447K |
| 代理商： | UPD30181AYF1-131-GA3-A |
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Data Sheet U16277EJ1V0DS
12
μ
PD30181A, 30181AY
(3/3)
Signal Name
I/O
Function
Alternate Function
SYSDIR
Note
O
Data bus isolation buffer direction control
This signal is valid only when accessing devices other than SDRAM or
SyncFlash memory devices. The signal is at high level during read
cycles and at low level during write cycles.
–
SYSEN#
Note
O
Enables data bus isolation buffer connection
This signal is set to high level during SDRAM and SyncFlash memory
cycles and is at low level when accessing any other devices.
–
DRQ(1:0)#
I
DMA service request signal
The DRQ(1:0)# signals are sampled at the rising edge of TClock. Be
sure to hold this signal at active level until a DMA request is
acknowledged. Set this signal as inactive when not using the DRQ(1:0)#
signals.
–
DAK(1:0)#
O
Enables DMA service request
This signal goes to active level when access to the target device occurs
via DMA transfer.
–
TC(1:0)#
I/O
DMA transfer completion signal (open drain)
This signal is driven at active level when a DMA transfer is completed.
During a transfer, this signal operates as a DMA stop request input
signal.
GPIO(53:52)
NMI#
I
Non-maskable interrupt input
This is an interrupt request signal that cannot be masked in relation to the
CPU core. When the V
R
4181A starts normally and the MPOWER signal
is at high level, input from the NMI# pin is connected to the CPU core via
the ICU. While the MPOWER signal is at low level, input to the NMI# pin
is monitored by the PMU as a source of NMI shutdowns.
–
Note
The SYSEN# and SYSDIR signals are buffer control signals used to isolate the SDRAM and SyncFlash
memory buses from other low-speed device buses. Isolating high-speed memory access paths from other
devices reduces the load on the system bus between the V
R
4181A and the SDRAM or SyncFlash
memory. When using the system bus isolation buffer, the correspondence between the SYSEN# and
SYSDIR signals and the data bus isolation status is as shown below.
SYSEN#
SYSDIR
Bus Operation
0
0
Enables connection via data bus isolation buffer
Write cycle for ROM, flash memory, SRAM, ISA device, CompactFlash/PC
Card, or other general-purpose device
Hibernate mode
0
1
Enables connection via data bus isolation buffer
Read cycle for ROM, flash memory, SRAM, ISA device, CompactFlash/PC
Card, or general-purpose device
1
0
Disables connection via data bus isolation buffer
Read/write cycle for SDRAM or SyncFlash memory
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