參數(shù)資料
型號(hào)： UPD30181AYF1-131-GA3-A
廠商： NEC Corp.
英文描述： 64-/32-BIT MICROPROCESSOR
中文描述： 64-/32-BIT微處理器
文件頁數(shù)： 29/72頁
文件大?。?/td> 447K
代理商： UPD30181AYF1-131-GA3-A
Data Sheet U16277EJ1V0DS
29
μ
PD30181A, 30181AY
(4/7)
Pin Name
(Signal Name)
Alternate-
Function Pin
Name (Alternate
Signal Name)
During RTC
Reset
After RTC Reset
After Reset by
RSTSW or
Watchdog Timer
In Suspend
Mode
In Hibernate
Mode or During
Shutdown by
HALTimer
UDN
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
BITCLK
SCLK, CTS2#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SYNC
WS, RTS2#,
DIVMODE1
Note 1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SDATAOUT
SDO, DTR2#,
DIVMODE0
Note 1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SDATAIN
SDI, DCD2#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SRESET#
DSR2#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCLK
BITCLK, CTS2#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
WS
SYNC, RTS2#,
DIVMODE1
Note 1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SDO
SDATAOUT,
DTR2#,
DIVMODE0
Note 1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SDI
SDATAIN,
DCD2#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
KSCAN11,
GPIO23
Hi-Z
Hi-Z
Hi-Z
Note 2
Hi-Z
SI
KSCAN10,
GPIO22
Hi-Z
Hi-Z
Hi-Z
Note 2
Hi-Z
SO
KSCAN9,
GPIO21
Hi-Z
Hi-Z
Hi-Z
Note 2
Hi-Z
FRM
KSCAN8,
GPIO20
Hi-Z
Hi-Z
–
Note 2
Hi-Z
RxD0
–
Hi-Z
Hi-Z
–
–
Hi-Z
TxD0
CLKSEL2
Note 3
Hi-Z
1
Note 2
1
RTS0#
GPIO19,
CLKSEL1
Note 3
Hi-Z
1
Note 2
1
CTS0#
GPIO18
Hi-Z
Hi-Z
–
–
Hi-Z
Notes 1.
The input level is sampled when the RTCRST# signal has changed to high level in order to set the
division ratio for the CPU core’s pipeline reference clock (AClock) and the peripheral system bus’s
reference clock (TClock).
2.
The status in the previous Fullspeed mode is retained.
3.
The input level is sampled when the RTCRST# signal has changed to high level in order to set the
frequency of the CPU core’s pipeline reference clock (AClock).
Remarks 1.
0: Low level, 1: High level, Hi-Z: High impedance
2.
When a pin has high impedance, the buffer’s input enable setting is OFF. Leakage current will not
occur even when an intermediate level is applied.
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