- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384042 > UPD30181AYF1-131-GA3 (NEC Corp.) 64-/32-BIT MICROPROCESSOR PDF資料下載
參數(shù)資料
| 型號： | UPD30181AYF1-131-GA3 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-/32-BIT MICROPROCESSOR |
| 中文描述： | 64-/32-BIT微處理器 |
| 文件頁數(shù)： | 21/72頁 |
| 文件大?。?/td> | 447K |
| 代理商： | UPD30181AYF1-131-GA3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
Data Sheet U16277EJ1V0DS
21
μ
PD30181A, 30181AY
(16) Debug interface signals
Signal Name
I/O
Function
Alternate Function
JTCK
I
N-Wire clock
–
JTMS
I
N-Wire mode select signal
This signal selects N-Wire serial transfer mode.
–
JTDI/RMODE#
I
N-Wire input data/N-Wire reset mode select signal
This pin functions alternately as RMODE# and JTDI. When JTRST# is
active it functions as RMODE#, and when JTRST# is inactive it functions
as JTDI.
RMODE# input
When JTRST# is active, this pin is the reset mode pin. The initial value
for a debug reset is determined by the level of this signal. A debug
reset is a reset of the processor, and there are two types: a debug cold
reset and a debug soft reset. This serves the same function as Cold
Reset input and Soft Reset input from various target systems.
0: Sets debug reset as valid and resets CPU core
1: Sets debug reset as invalid and does not reset CPU core
JTDI input
When the JTRST# signal is inactive, this pin operates as the N-Wire
serial data input.
–
JTDO
O
N-Wire serial data output
–
JTRST#
I
N-Wire reset signal
–
BKTGIO#
I/O
N-Wire break trigger I/O
BKTGIO#: When used for input setting
When JTRST# is inactive and BKTGIO# is used for input setting, this
pin is the event trigger/break request input pin. When break requests
are valid, setting BKTGIO# to low level stops execution of user
programs in normal mode and forcibly shifts the processor to debug
mode. After BKTGIO# goes to low level in debug mode, break requests
are retained until the processor is restored to normal mode.
0: Requests break and forcibly shifts processor to debug mode
1: Retains current status of processor
BKTGIO#: When used for output setting
When JTRST# is inactive and BKTGIO# is used for output setting, this
pin is the event trigger/break output pin. When the processor is
operating in normal mode and an event is detected that meets any of
the conditions for a hardware breakpoint (instruction address breakpoint
or data access breakpoint), an event trigger is output from BKTGIO# as
a low level signal (one pulse) and detection of the event is reported to
the external debugging tool. Finally, after the event trigger is output, all
detected events are reported as one event trigger. When the processor
is shifted to debug mode, output continues at low level and all
previously non-reported events are not reported.
0: Hardware breakpoint was detected
The processor is shifted to debug mode.
1: The processor is in normal mode.
–
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD30181AYF1-131-GA3-A | 64-/32-BIT MICROPROCESSOR |
| UPD30181GM-66-8ED | 64-/32-Bit Microprocessor |
| UPD3570 | UPD3570 2560-BIT CCD LINEAR IMAGE SENSOR |
| UPD3570D | UPD3570 2560-BIT CCD LINEAR IMAGE SENSOR |
| UPD3571 | 5000 BIT CCD LINEAR IMAGE SENSOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD30181AYF1-131-GA3-A | 制造商:Renesas 功能描述:MPU VR4181A RISC 32-Bit/64-Bit 0.25um 131MHz 3.3V 240-Pin FBGA |
| UPD30181GM-66-8ED | 制造商:NEC 制造商全稱:NEC 功能描述:64-/32-Bit Microprocessor |
| UPD30200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VR4300(TM).VR4305(TM).VR4310(TM) User＇s Manual | User＇s Manual[08/2000] |
| UPD30200GD-100MBB | 制造商:NEC Electronics Corporation 功能描述: |
| UPD30200GD-100-MBB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。