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參數(shù)資料
| 型號： | UPD30181AYF1-131-GA3 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-/32-BIT MICROPROCESSOR |
| 中文描述： | 64-/32-BIT微處理器 |
| 文件頁數(shù)： | 16/72頁 |
| 文件大?。?/td> | 447K |
| 代理商： | UPD30181AYF1-131-GA3 |
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Data Sheet U16277EJ1V0DS
16
μ
PD30181A, 30181AY
(6) CompactFlash/PC Card/IDE (ATA) interface signal
Signal Name
I/O
Function
Alternate Function
CF1_CD(2:1)#
I
CompactFlash/PC Card (slot 1) detection signal
FPD(11:10),
GPIO(47:46)
CF1_CE(2:1)#
O
CompactFlash/PC Card (slot 1) enable signal
FPD(13:12),
GPIO(49:48)
CF1_STSCHG#
I
CompactFlash/PC Card (slot 1) status change signal
FPD14, GPIO50
CF1_READY
I
CompactFlash/PC Card (slot 1) ready signal
FPD15, GPIO51
CF1_RESET
O
CompactFlash/PC Card (slot 1) reset signal
DBUS32
CF1_DIR
O
CompactFlash/PC Card (slot 1) data bus direction control signal
KPORT4,
GPIO39
CF1_EN#
O
CompactFlash/PC Card (slot 1) buffer enable signal
KPORT5,
GPIO38
CF1_VCCEN#
O
CompactFlash/PC Card (slot 1) V
CC
enable signal
KSCAN4,
GPIO37
CF0_CD(2:1)#
I
CompactFlash/PC Card (slot 0) detection signal
GPIO(36:35)
CF0_IOIS16#
I
CompactFlash/PC Card (slot 0) I/O 16-bit bus signal
GPIO34
CF_WAIT#
I
CompactFlash/PC Card (slots 0, 1) wait signal
GPIO33
CF0_CE(2:1)#
O
CompactFlash/PC Card (slot 0) enable signal
GPIO(32:31)
CF0_STSCHG#
I
CompactFlash/PC Card (slot 0) status change signal
GPIO30
CF0_READY
I
CompactFlash/PC Card (slot 0) ready signal
GPIO29
CF0_RESET
O
CompactFlash/PC Card (slot 0) reset signal
GPIO28
CF0_DIR
O
CompactFlash/PC Card (slot 0) data bus direction control signal
GPIO27
CF0_EN#
O
CompactFlash/PC Card (slot 0) buffer enable signal
GPIO26
CF_REG#
O
CompactFlash/PC Card (slots 0, 1) register select signal
GPIO25
CF0_VCCEN#
O
CompactFlash/PC Card (slot 0) V
CC
enable signal
GPIO24
Cautions 1. Be sure to use MEMRD#, MEMWR#, IORD#, and IOWR# respectively as CompactFlash/PC
Card access strobe signals OE#, WE#, IORD#, and IOWR#.
2. The CF0_EN#, CF1_EN#, CF0_DIR, and CF1_DIR signals are used to control the buffer that
isolates the CompactFlash/PC Card’s bus from other device’s buses. This isolation of the
CompactFlash/PC Card’s bus enables hot plug-in support. The following table lists the
correspondence between the CF0_EN#, CF1_EN#, CF0_DIR, and CF1_DIR signals and data
bus isolation statuses when using the data bus isolation buffer.
CF0_EN#,
CF1_EN#
CF0_DIR,
CF1_DIR
Operation of Bus
0
0
Enable connection via data bus isolation buffer
Write cycle to CompactFlash/PC Card
0
1
Enable connection via data bus isolation buffer
Read cycle to CompactFlash/PC Card
1
– (Undefined)
Disable connection via data bus isolation buffer
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| UPD30181AYF1-131-GA3-A | 64-/32-BIT MICROPROCESSOR |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD30181AYF1-131-GA3-A | 制造商:Renesas 功能描述:MPU VR4181A RISC 32-Bit/64-Bit 0.25um 131MHz 3.3V 240-Pin FBGA |
| UPD30181GM-66-8ED | 制造商:NEC 制造商全稱:NEC 功能描述:64-/32-Bit Microprocessor |
| UPD30200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VR4300(TM).VR4305(TM).VR4310(TM) User＇s Manual | User＇s Manual[08/2000] |
| UPD30200GD-100MBB | 制造商:NEC Electronics Corporation 功能描述: |
| UPD30200GD-100-MBB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
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