參數(shù)資料
型號： UPD30181AYF1-131-GA3
廠商： NEC Corp.
英文描述： 64-/32-BIT MICROPROCESSOR
中文描述： 64-/32-BIT微處理器
文件頁數(shù)： 17/72頁
文件大?。?/td> 447K
代理商： UPD30181AYF1-131-GA3
Data Sheet U16277EJ1V0DS
17
μ
PD30181A, 30181AY
(7) USB (host/function) interface signals
Signal Name
I/O
Function
Alternate Function
CLK48
I
USB clock (48 MHz)
–
UHDP
I/O
USB host serial data (+) signal
Be sure to connect a 22
resistor in series for impedance matching.
–
UHDN
I/O
USB host serial data (–) signal
Be sure to connect a 22
resistor in series for impedance matching.
–
UPON
O
USB host route hub power control signal
–
UOC
I
USB host route hub overcurrent input signal
–
UDP
I/O
USB function serial data (+) signal
Be sure to connect a 22
resistor in series for impedance matching.
–
UDN
I/O
USB function serial data (–) signal
Be sure to connect a 22
resistor in series for impedance matching.
–
(8)
AC97/I
2
S stereo audio interface signals
Signal Name
I/O
Function
Alternate Function
BITCLK/SCLK
I/O
Bit clock input (12.288 MHz) for AC97/input or output of I
(maximum frequency during input: 6.144 MHz).
When used as the SCLK signal, this signal is output by the V
R
4181A
when the I2SU is in master mode and is input from an external source in
slave mode.
2
S clock
CTS2#
SYNC/WS
I/O
Synchronous clock output for AC97/input or output of I
signal
When used as the WS signal, this signal is output by the V
R
4181A when
the I2SU is in master mode and is input from an external source in slave
mode.
2
S word select
RTS2#,
DIVMODE1
SDATAOUT/SDO
O
Serial data output signal for AC97/serial data output signal for I
2
S
DTR2#,
DIVMODE0
SDATAIN/SDI
I
Serial data input signal for AC97/serial data input signal for I
2
S
DCD2#
SRESET#
O
Reset signal for AC97
DSR2#
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