參數(shù)資料
型號： UPD30181AYF1-131-GA3
廠商： NEC Corp.
英文描述： 64-/32-BIT MICROPROCESSOR
中文描述： 64-/32-BIT微處理器
文件頁數(shù)： 15/72頁
文件大小： 447K
代理商： UPD30181AYF1-131-GA3
Data Sheet U16277EJ1V0DS
15
μ
PD30181A, 30181AY
(5) LCD interface signals
Signal Name
I/O
Function
Alternate Function
DCLK/SHCLK
O
Dot clock (DCLK) for TFT/shift clock (SHCLK) for STN
–
HSYNC/LOCLK
O
Horizontal sync signal for TFT/load clock for STN
NWIREEN
VSYNC/FLM
O
Vertical sync signal for TFT/first line clock for STN
BMODE1
ENAB/M
O
Display enable signal for TFT/M clock for STN
BMODE0
FPD15
O
LCD display data
CF1_READY,
GPIO51
FPD14
O
LCD display data
CF1_STSCHG#,
GPIO50
FPD(13:12)
O
LCD display data
CF1_CE(2:1)#,
GPIO(49:48)
FPD(11:10)
O
LCD display data
CF1_CD(2:1)#,
GPIO(47:46)
FPD(9:4)
O
LCD display data
GPIO(45:40)
FPD(3:0)
O
LCD display data
–
VPBIAS
O
LED bias power control
This signal can be used as a general-purpose output when not using the
LCD controller.
GPO63
VPLCD
O
LCD logic power control
This signal can be used as a general-purpose output when not using the
LCD controller.
GPO62
Caution
The connection between the FPD(15:0) of the V
R
4181A and LCD panel data line corresponds to
the panel data width, as shown below.
V
R
4181A
STN Panel Data
(4 Bits)
STN Panel Data
(8 Bits)
TFT Panel Data
(12 Bits)
TFT Panel Data
(16 Bits)
FPD0
Data line 0
Data line 0
Data line (B0)
Data line (B0)
FPD1
Data line 1
Data line 1
Data line (B1)
Data line (B1)
FPD2
Data line 2
Data line 2
Data line (B2)
Data line (B2)
FPD3
Data line 3
Data line 3
Data line (B3)
Data line (B3)
FPD4
–
Data line 4
Data line (G0)
Data line (B4)
FPD5
–
Data line 5
Data line (G1)
Data line (G0)
FPD6
–
Data line 6
Data line (G2)
Data line (G1)
FPD7
–
Data line 7
Data line (G3)
Data line (G2)
FPD8
–
–
Data line (R0)
Data line (G3)
FPD9
–
–
Data line (R1)
Data line (G4)
FPD10
–
–
Data line (R2)
Data line (G5)
FPD11
–
–
Data line (R3)
Data line (R0)
FPD12
–
–
–
Data line (R1)
FPD13
–
–
–
Data line (R2)
FPD14
–
–
–
Data line (R3)
FPD15
–
–
–
Data line (R4)
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