參數(shù)資料
型號(hào)： UPD30181AYF1-131-GA3
廠商： NEC Corp.
英文描述： 64-/32-BIT MICROPROCESSOR
中文描述： 64-/32-BIT微處理器
文件頁(yè)數(shù)： 39/72頁(yè)
文件大?。?/td> 447K
代理商： UPD30181AYF1-131-GA3
Data Sheet U16277EJ1V0DS
39
μ
PD30181A, 30181AY
(2) Pins of I/O circuit types B and G
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
OH2
Pins of type B
Note 1
, I
OH
= –2 mA
0.8V
DD33
V
Output voltage, high
V
OH_USB
Pins of type G
Note 2
, R
PD
= 15 k
2.8
3.6
V
V
OL2
Pins of type B
Note 1
, I
OL
= 2 mA
0.4
V
Output voltage, low
V
OL_USB
Pins of type G
Note 2
, R
PU
= 1.5 k
0.3
V
V
IH2
Pins of type B
Note 1
0.75V
DD33
V
DD33
+
0.3
V
Input voltage, high
V
IH_USB
Pins of type G
Note 2
, single end
2.0
V
V
IL2
Pins of type B
Note 1
0.3
0.6
V
Input voltage, low
V
IL_USB
Pins of type G
Note 2
, single end
0.8
V
Hysteresis voltage
Note 3
V
H
Pins of type B
Note 1
0.17V
DD33
V
Output cross level
Note 4
V
CRS_USB
Pins of type G
Note 2
1.3
2.0
V
Differential input
sensitivity
Note 4
V
DI_USB
Pins of type G
Note 2
0.2
V
Differential input common
mode range
Note 4
V
CM_USB
Pins of type G
Note 2
, V
DI
< 200 mV
0.8
2.5
V
External pull-up resistor
R
PU
Pins of type G
Note 2
1.425
1.575
k
External pull-down resistor
R
PD
Pins of type G
Note 2
14.25
15.75
k
External resistor for
impedance adjustment
Note 5
R
S
Pins of type G
Note 2
20.9
23.1
Notes 1.
Applies to the following pins.
POWER, RSTSW#, RTCRST#, CF1_RESET/DBUS32, RxD0, TxD0/CLKSEL2, RxD2/IRDIN,
TxD2/IRDOUT/MIPS16EN, CTS2#/BITCLK/SCLK, DTR2#/SDATAOUT/SDO/DIVMODE0,
RTS2#/SYNC/WS/DIVMODE1, DCD2#/SDATAIN/SDI, DSR2#/SRESET#, UOC,
CF1_DIR/KPORT4/GPIO39, CF1_EN#/KPORT5/GPIO38, CF1_VCCEN#/KSCAN4/GPIO37,
CF0_CD2#/GPIO36, CF0_CD1#/GPIO35, CF0_IOIS16#/GPIO34, CF_WAIT#/GPIO33,
CF0_CE2#/GPIO32, CF0_CE1#/GPIO31, CF0_STSCHG#/GPIO30, CF0_READY/GPIO29,
CF0_RESET/GPIO28, CF0_DIR/GPIO27, CF0_EN#/GPIO26, CF_REG#/GPIO25,
CF0_VCCEN#/GPIO24, SCK/KSCAN11/GPIO23, SI/KSCAN10/GPIO22, SO/KSCAN9/GPIO21,
FRM/KSCAN8/GPIO20, RTS0#/GPIO19/CLKSEL1, CTS0#/GPIO18, DTR0#/RTS1#/GPIO17/CLKSEL0,
DCD0#/GPIO16, DSR0#/CTS1#/GPIO15, RxD1/SCL1/GPIO14, TxD1/SDA1/GPIO13,
SCL0/KPORT7/GPIO12, SDA0/KPORT6/GPIO11, PWM(2:0)/KSCAN(5:7)/GPIO(10:8),
KPORT(3:0)/GPIO(7:4), KSCAN(3:0)/GPIO(3:0)
2.
Applies to the UHDP, UHDN, UDP, and UDN pins
3.
Hysteresis voltage: Difference between the minimum voltage at which the high level of a Schmitt input
signal is not recognized when the signal goes from low to high and the maximum voltage at which the
low level is not recognized when the signal goes from high to low.
4.
Precision tests have not been performed. Only guaranteed as design characteristics.
5.
The recommended value is 22
.
Remark
For details of the I/O circuits, refer to
1.4 Pin I/O Circuits
.
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