
TMS320AV110
MPEG AUDIO DECODER
SCSS013A – MAY 1993 – REVISED SEPTEMBER 1993
28
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
RESET, reset decoder, (40h)
Resets the decoder. Equivalent to the assertion of the RESET input except that the MUTE and PLAY registers
are not affected. Resets the interrupt register, locates and sizes external memory, flushes all data buffers, and
then clears the reset register. A pin RESET is required after powerup.
0 = No reset, do not write this value
1 = Reset
RESTART, flush data buffers, (42h)
Flushes all data buffers. Has no effect on control registers, does not test memory, and does not clear the EOS
interrupt request register bit. Upon completion, RESTART is cleared by the ’AV110.
0 = No restart
1 = Restart
SRC (32:0), system reference clock, 32, 31:24, 23:16, 15:8, 7:0 (76-75-74-73-72h)
Contains the value of the system reference clock. This register is updated every time an SRC is detected,
provided the respective interrupt is enabled in register INTR_EN.
SIN_EN, serial input enable, (70h)
0 = Parallel data Input
1 = Serial data Input
SKIP, skip next audio frame, (32h)
The decoder skips (ignores) the next audio frame and resets the SKIP register. A zero should be written to this
register during initialization.
0 = No skip
1 = Skip
STR_SEL, input configuration, 1:0 (36h)
00 = MPEG audio stream
01 = MPEG packet stream
10 = MPEG system stream
11 = Audio bypass
SYNC_ECM, synchronization error handling, 1:0 (2Ch)
00 = Ignore error
01 = Mute on synchronization error
10 = Repeat last valid frame. Repeat once if layer 2, three times if layer 1, mute thereafter. Valid with external
memory only.
11 = Skip invalid frame
SYNC_LCK, good synchronization words, 1:0 (28h)
Contains the number of additional good-synchronization words to be found, after the first good-synchronization
word, before changing to the locked state.