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參數(shù)資料
| 型號(hào)： | TMS320AV110 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MPEG Audio Decoder(MPEG音頻譯碼器) |
| 中文描述： | MPEG音頻解碼器（的MPEG音頻譯碼器） |
| 文件頁數(shù)： | 13/38頁 |
| 文件大?。?/td> | 796K |
| 代理商： | TMS320AV110 |
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TMS320AV110
MPEG AUDIO DECODER
SCSS013C – MAY 1993 – REVISED AUGUST 1995
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
wait timing
The WAIT output is used by the ’AV110 to control memory-mapped communications between the host and the
’AV110. The WAIT line can be shared among devices and therefore it is in the high-impedance state when not
in use. The WAIT line is driven within 20 ns of the DCS assertion (falling edge) and is in the high-impedance
state within 20 ns of the release of the DCS line.
register accesses and data inputs
If register accesses and data inputs (serial or parallel) are performed back-to-back, the timing relationships
shown in Figure 5 must be met. These setup times provide sufficient time to assure that these operations do
not interfere with each other.
DCS
DSTRB
I
tsu8
tsu9
Figure 5. Data-Strobe Timing
reset operations
There are no default settings of the control and status registers; the audio decoder requires that the host set
all control register settings using register-access mode. Reset can be initiated by the RESET input or by the
host writing to the RESET register via register access. (Upon power up, the RESET input must be used.)
Figure 6 shows RESET, BOF, IRQ, and PTS timing.
PTS
RESET
IRQ
BOF
O
I
tw4
td3
td2
td4
NOTE: This diagram shows individual signal timing only. The signals are shown together for convenience and do not show their relationship.
Figure 6. RESET, BOF, IRQ, and PTS Signal Timing
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