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參數(shù)資料
| 型號(hào)： | TMS320AV110 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MPEG Audio Decoder(MPEG音頻譯碼器) |
| 中文描述： | MPEG音頻解碼器（的MPEG音頻譯碼器） |
| 文件頁數(shù)： | 25/38頁 |
| 文件大?。?/td> | 796K |
| 代理商： | TMS320AV110 |
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TMS320AV110
MPEG AUDIO DECODER
SCSS013C – MAY 1993 – REVISED AUGUST 1995
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ANC, ancillary data buffer, 31:24, 23:16, 15:8, 7:0 (09-08-07-06h)
A FIFO that holds the last 32 bits of ancillary data in the data stream. The ANC is updated only when the
corresponding IRQ is enabled and after the ANC_AV register has been read.
ANC_AV, ancillary data available, 5:0 (6Ch)
Holds the number of bits of ancillary data available in the ANC buffer. This register must be read by the host
before reading the ANC register.
ATTEN_L, left channel attenuator, 5:0 (1Eh)
Minimum = 0, maximum = 63 in 2-dB steps.
ATTEN_R, right channel attenuator, 5:0 (20h)
Minimum = 0, maximum = 63 in 2-dB steps.
AUD_ID, audio stream, 4:0 (22h)
Specifies 1 of 32 possible audio streams in the MPEG system or packet layer to be decoded. AUD_ID is ignored
if AUD_ID_EN is not asserted.
AUD_ID_EN, audio stream ID enable, (24h)
0 = Audio stream ID is ignored.
1 = Audio stream ID is decoded and only the selected stream is decoded.
BALE_LIM, buffer almost empty limit, 14:8, 7:0 (69-68h)
Sets the almost empty limit for the input buffer. Values may be from 0000h to 6600h for DRAM (0000h to 003Dh
for SRAM) and specifies the number of 32-bit words in the input buffer before INTR bit 3 is set. When using the
internal 256-byte SRAM for the input buffer, it is recommended that REQ be monitored rather than the
BALE_LIM and BALF_LIM interrupts.
BALF_LIM, buffer almost full limit, 14:8, 7:0 (6B-6Ah)
Sets the almost full limit for the input buffer. Values may be from 0000h to 6600h for DRAM (0000h to 003Dh
for SRAM) and specifies the number of 32-bit words in the input buffer before INTR bit 4 is set.
BUFF, input buffer word counter, 14:8, 7:0 (13-12h)
Contains the amount of data being held in the input buffer in 32-bit words. Updated after every 32-bit data write
to the input. (The input buffer refers to either the internal 256-byte SRAM or the optional DRAM.)
CRC_ECM, CRC error handling, 1:0 (2Ah)
00 = CRC detection is disabled.
01 = Mute on CRC error
10 = Repeat last valid frame. Repeat once if layer 2, three times if layer 1, mute thereafter. Valid with external
memory only.
11 = Skip invalid frame
DATAIN, audio data input register, 7:0 (18h)
The audio data input register is used only if data is input in memory-mapped mode.
DIF, 18-bit data in front register, (6Fh)
Specifies where 18-bit PCM data output is located with respect to LRCLK and SCLK (see Figure 9 and
Figure 10).
0 = Data is in the back or last 18 SCLKs.
1 = Data is in the front or first 18 SCLKs.
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