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參數(shù)資料
| 型號： | TMS320AV110 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MPEG Audio Decoder(MPEG音頻譯碼器) |
| 中文描述： | MPEG音頻解碼器（的MPEG音頻譯碼器） |
| 文件頁數(shù)： | 27/38頁 |
| 文件大小： | 796K |
| 代理商： | TMS320AV110 |
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TMS320AV110
MPEG AUDIO DECODER
SCSS013C – MAY 1993 – REVISED AUGUST 1995
27
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
IRC_LOAD, load internal reference clock, (7Eh)
0 = No action on IRC
1 = IRC counter is loaded with the decoded system reference clock (SRC) value. IRC_LOAD is then reset.
LATENCY, decoder latency selection, (3Ch)
0 = Low latency, less than 10 ms
1 = High latency, more than one frame time. High latency has more robust synchronization detection than low
latency.This mode is provided to allow for the detection of a possible loss of synchronization prior to
decoding each frame. (Synchronization look ahead). High latency is valid only with external DRAM.
MUTE, muting, (30h)
Enables the output of muted PCM data. Muting is enabled if eitherthis register or the MUTE input line is asserted.
Muting does not affect the audio decoding process.
0 = PCM data not muted
1 = PCM data muted
PCM_DIV, divider value, 5:0 (6Eh)
Sets the PCMCLK divider value to an integer in the range of 1 to 32.
PCM_18, output precision select, (16h)
0 = 16-bit PCM output
1 = 18-bit PCM output
PCM_FS, sampling rate, 1:0 (44h)
00 = 44.1 kHz
01 = 48 kHz
10 = 32 kHz
11 = Reserved
PCM_ORD, output order select, (38h)
0 = Most significant bit output first
1 = Least significant bit output first
PLAY, output decoded audio data, (2Eh)
Enables the output of decoded audio data. Output is enabled only if boththis register and the PLAY input line
are asserted. Does not affect the output of muted audio. When both PLAY and MUTE are deasserted, outputs
SCLK and LRCLK stop switching and PCMDATA is forced low.
0 = Don’t play
1 = Play
PTS, presentation time stamp, 32, 31:24, 23:16, 15:8, 7:0 (66-65-64-63-62h)
Contains the PTS associated with the frame currently being decoded. If the corresponding PTS interrupt is
enabled, the contents are retained until the register MSB is read.
REPEAT, repeat next audio frame, (34h)
The decoder repeats the next audio frame and resets the REPEAT register. If external memory (DRAM) is not
present, a muted frame is inserted. A zero should be written to this register during initialization.
0 = No repeat
1 = Repeat
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