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參數(shù)資料
| 型號： | TMS320AV110 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MPEG Audio Decoder(MPEG音頻譯碼器) |
| 中文描述： | MPEG音頻解碼器（的MPEG音頻譯碼器） |
| 文件頁數(shù)： | 22/38頁 |
| 文件大?。?/td> | 796K |
| 代理商： | TMS320AV110 |
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TMS320AV110
MPEG AUDIO DECODER
SCSS013C – MAY 1993 – REVISED AUGUST 1995
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ancillary data handling
The handling of ancillary data is controlled by the contents of the ancillary data register (ANC) and the ancillary
data available (ANC_AV) registers in conjunction with interrupt request bits 6 and 7. If interrupts 6 and 7 are
masked, ancillary data is ignored. If interrupt 6 is enabled, incoming ancillary data is placed in an internal buffer.
This buffer is treated as a FIFO; it always holds the last 32 bits. If interrupt 7 is masked, the oldest data is replaced
with new data on a bit-by-bit basis. If interrupt 7 is enabled, a full interrupt is generated when the FIFO is full
and further processing of audio data is halted until either the data is read or interrupt 7 is masked.
The ancillary data available (ANC_AV) register always holds the number of bits available in the ancillary buffer.
Interrupt 6 is generated when either 16 bits of data are available or the end of a frame is reached. Interrupt 7
is generated when 32 bits of data are available, and all processing stops until the ANC_AV register is read.
Before reading the ANC register, the host must read the ANC_AV register to determine the number of valid
ancillary data bits available. The register must be read, even if the number of valid bits is known. When the
ANC_AV register is read, the contents of the internal ancillary FIFO are transferred to the ANC register and the
ANC_AV register is cleared. The ancillary data bits are loaded into the least significant bits of the ANC register.
The host can then read the specified number of bits by accessing the ANC register addresses. This sequence
ensures that the data is available for reading without conflict with any additional data coming in. If the ANC_AV
register is read a second time, the ANC register is updated with any new data, whether the host has completed
reading the ANC register or not. All 32 bits of the ANC register are overwritten each time ANC_AV is read.
external DRAM
The ’AV110 is designed to interface with a fast page-mode 256K
×
4 DRAM (100 ns maximum). The ’AV110 uses
only the enhanced page-mode read and write cycles and the automatic CAS-before-RAS refresh cycle timing.
The ’AV110 provides a 665-
μ
s minimum power-up pause with 16 initialization cycles. The ’AV110 is designed
to support a 1M
×
4 DRAM (TMS44400) in the event that the 1M
×
4 DRAM becomes less expensive than the
256K
×
4. When a 1M
×
4 DRAM is used, only 256K
×
4 of the 1M
×
4 is utilized by the ’AV110. Upon power up,
the ’AV110 determines if external DRAM is present. If a DRAM is present, the DRAM_EXT register is set and
the ’AV110 uses it as an input buffer. The following lists the trade-offs of using external DRAM versus internal
SRAM only for the input buffer.
with DRAM
–
–
–
–
Audio can be buffered for audio/video synchronization purposes
Allows more robust error concealment
Both register skip and register repeat functions are supported
Synchronization look ahead (high latency) is supported
without DRAM
–
–
–
–
Input buffer is only 256 bytes
A register repeat command causes a muted frame to be inserted
No synchronization look ahead (low latency)
Buffer almost empty (BALE) and buffer almost full (BALF) interrupts still work, but REQ should be
monitored
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS320AV120 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Audio Decoder & Support |
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| TMS320AV220PCM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Audio/Video Decoder for MPEG |
| TMS320AV410 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Encoder Circuit |
| TMS320AV410PJM | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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