參數(shù)資料
型號(hào)： TMS320AV110
廠商： Texas Instruments, Inc.
英文描述： MPEG Audio Decoder(MPEG音頻譯碼器)
中文描述： MPEG音頻解碼器（的MPEG音頻譯碼器）
文件頁(yè)數(shù)： 14/38頁(yè)
文件大?。?/td> 796K
代理商： TMS320AV110
TMS320AV110
MPEG AUDIO DECODER
SCSS013C – MAY 1993 – REVISED AUGUST 1995
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
reset and restart actions
Reset, initiated either by the RESET input or a register-access write initiates the following actions:
–
The reset (RESET) register is set.
–
The REQ output goes high.
–
The interrupt request (INTR) and interrupt enable (INTR_EN) registers are cleared.
–
The buffer (BUFF) register is cleared.
–
The DRAM goes through power-up refresh cycling (pin reset only).
–
All data buffers are cleared. This takes multiple clock cycles.
–
The ’AV110 checks for the presence of external DRAM and the size of the external DRAM.
–
The MUTE and PLAY registers are deasserted (pin reset only). This inhibits the output clocks, LRCLK
and SCLK, and zeros the data out.
–
The PCM_DIV register is affected by pin reset; otherwise all other control registers remain in their
existing states.
–
Register accesses by the host interface are disabled only when RESET is low. Audio data can be input
only after REQ has gone low.
–
The ’AV110 terminates the reset cycle. It clears the reset register and REQ goes low. Reset cycles last
approximately 700
μ
s without DRAM and 3.7 ms with DRAM (OSCIN 24 MHz).
Restart can be initiated by the host writing to the RESTART register (flush data buffers), which starts the
following actions:
–
The RESTART register is set.
–
The REQ output goes high.
–
The interrupt registers (INTR and INTR_EN) are cleared.
–
The BUFF register is cleared.
–
The DRAM does not go through power-up refresh cycling.
–
All data buffers are cleared.
–
MUTE, PLAY, and all other control and status registers remain at their existing state.
–
Register accesses by the host interface are not disabled. However, when REQ is high, the host cannot
register-access the primary data input.
–
The ’AV110 terminates the restart cycle and clears the RESTART register. REQ goes low.
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