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參數(shù)資料
| 型號： | TMS320AV110 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MPEG Audio Decoder(MPEG音頻譯碼器) |
| 中文描述： | MPEG音頻解碼器（的MPEG音頻譯碼器） |
| 文件頁數(shù)： | 26/38頁 |
| 文件大?。?/td> | 796K |
| 代理商： | TMS320AV110 |
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TMS320AV110
MPEG AUDIO DECODER
SCSS013A – MAY 1993 – REVISED SEPTEMBER 1993
26
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DMPH, deemphasis mode,1:0 (46h)
00 = None
01 = 50 /15 microseconds
10 = Reserved
11 = CCITT J.17
DRAM_EXT, memory status, (3Eh)
0 = Integral 256-byte SRAM only is being used for the input buffer.
1 = External DRAM memory only is being used for the input buffer. This bit is set by the ’AV110 during power
up when external DRAM is present.
FREE_FORM, free format frame length,
10:8, 7:0 (15-14h)
Frame length in free format decoding. Should be set to 0 if length is unknown.
HEADER, frame header, 31:24, 23:16, 15:8, 7:0 (61-60-5F-5Eh)
Contains the frame header currently being decoded. This register is updated only when corresponding interrupt
is enabled and the contents are retained until the register MSB has been read.
INTR, interrupt request register, 15:8, 7:0 (1B-1Ah)
BIT NO.
15-12
11
10
9
8
FUNCTION
SEE NOTE
—
2
3
3
3
Not used
Set when SRC is detected.
Set when deemphasis is changed.
Set when the sampling frequency is changed.
Set on PCM output buffer underflow
Set when ancillary data is full. Inhibits further placement of ancillary data into the FIFO until the
data is read .
Set when ancillary data is registered.
Set when CRC error is detected.
Set when the input buffer is over the BALF_LIM.
Set when the input buffer is below the BALE_LIM.
Set when a valid PTS has been registered.
Set when a valid header has been registered.
Set upon a change in the synchronization status
7
2
6
5
4
3
2
1
0
3
3
3
3
2
2
2
NOTES:
1. Cleared when the interrupt request register is read or upon RESET. This bit is
not
cleared by a RESTART
.
2. Cleared when the corresponding data register is read or upon RESET or RESTART. These interrupts must be cleared for additional
interrupts (of this type) to occur.
3. Cleared when the interrupt request register is read or upon RESET or RESTART.
INTR_EN, interrupt enable register, 15:8, 7:0 (1D-1Ch)
A 1 in any bit position will enable the corresponding bit in the INTR register.
IRC, internal reference clock, 32, 31:24, 23:16, 15:8, 7:0 (7C-7B-7A-79-78h)
Contains the value of the internal reference clock. This register is updated every time an SRC is detected (after
an IRC_LOAD) provided the SRC interrupt is enabled in register INTR_EN.
IRC_CNT, internal reference counter register, 32, 31:24, 23:16, 15:8, 7:0 (58-57-56-55-54h)
This register contains the present internal reference count and is updated continuously by the CLK90 input.
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