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參數(shù)資料
| 型號： | TMC22X5YA |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
| 中文描述： | 多標(biāo)準(zhǔn)數(shù)字視頻解碼器三線自適應(yīng)梳狀解碼器系列，8 |
| 文件頁數(shù)： | 68/84頁 |
| 文件大?。?/td> | 417K |
| 代理商： | TMC22X5YA |
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TMC22x5yA
PRODUCT SPECIFICATION
68
REV. 1.0.0 2/4/03
Serial Control Port (R-Bus)
In addition to the 12-wire parallel port, a 2-wire serial
control interface is provided, and active when SER is LOW.
Either port alone can control the entire chip. Up to eight
TMC22x5yA devices may be connected to the 2-wire serial
interface with each device having a unique address.
The 2-wire interface comprises a clock (SCL) and a bi-direc-
tional data (SDA) pin. The Decoder acts as a slave for receiv-
ing and transmitting data over the serial interface. When the
serial interface is not active, the logic levels on SCL and
SDA are pulled HIGH by external pull-up resistors.
Data received or transmitted on the SDA line must be stable
for the duration of the positive-going SCL pulse. Data on
SDA must change only when SCL is LOW. If SDA changes
state while SCL is HIGH, the serial interface interprets that
action as a start or stop sequence.
There are six components to serial bus operation:
Start signal
Slave address byte
Block Pointer
Base register address byte
Data byte to read or write
Stop signal
When the serial interface is inactive (SCL and SDA are
HIGH) communications are initiated by sending a start sig-
nal. The start signal is a HIGH-to-LOW transition on SDA
while SCL is HIGH. This signal alerts all slaved devices that
a data transfer sequence is coming.
The first eight bits of data transferred after a start signal com-
prise a seven bit slave address (the first seven bits) and a sin-
gle R/W bit (the eighth bit). The R/W bit indicates the
direction of data transfer, read from or write to the slave
device. If the transmitted slave address matches the address
of the device (set by the state of the SA
2-0
input pins in Table
20), the TMC22x5yA acknowledges by bringing SDA LOW
on the 9th SCL pulse. If the addresses do not match, the
TMC22x5yA does not acknowledge.
Figure 33. Microprocessor Parallel Port
–
Write Timing
Figure 34. Microprocessor Parallel Port
–
Read Timing
t
PWLCS
t
SA
t
SD
t
HA
t
HD
t
PWHCS
CS
65-22x5y-16
R/W
ADR
D
7-0
t
PWLCS
t
SA
t
DOM
t
HA
t
HOM
t
DOZ
t
PWHCS
CS
R/W
ADR
D
7-0
65-22x5y-17
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