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參數(shù)資料
| 型號： | TMC22X5YA |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
| 中文描述： | 多標(biāo)準(zhǔn)數(shù)字視頻解碼器三線自適應(yīng)梳狀解碼器系列，8 |
| 文件頁數(shù)： | 30/84頁 |
| 文件大?。?/td> | 417K |
| 代理商： | TMC22X5YA |
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TMC22x5yA
PRODUCT SPECIFICATION
30
REV. 1.0.0 2/4/03
Control Register De
fi
nitions
(continued)
Output Format Control (26)
7
6
5
4
3
2
1
0
Reserved
LDVIO
OPCKS
DPCEN
DPC
Reg
26
26
26
Bit
7-6
5
4
Name
Reserved
LDVIO
OPCKS
Description
Reserved, set to zero.
LDV clock select.
LDV is an output when LOW and an input when HIGH
Output clock select.
The output data are clocked by the CLOCK pin when
LOW and by the LDV pin when HIGH.
DPC enable.
When HIGH on the TMC22153A, the Decoder Product Code is
enabled: a value written into DPC determines the decoder product emulated
by the TMC22153A. In all other versions of the decoder, DPC is read-only,
and returns the code of the particular encoder version installed.
Decoder product code
26
3
DPCEN
26
2-0
DPC
Read/Write in the TMC22153A only. Read-only in all other devices.
Buffered register set 1 (27)
Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
SG1
7
SG1
6
SG1
5
SG1
4
SG1
3
SG1
2
SG1
1
SG1
0
Reg
27
Bit
7-0
Name
SG1
7-0
Description
Msync gain, 8 lsbs.
Bottom 8 bits of the mixed sync scalar
lsb = 1/256
Buffered register set 1 (28)
Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
YG1
7
YG1
6
YG1
5
YG1
4
YG1
3
YG1
2
YG1
1
YG1
0
Reg
28
Bit
7-0
Name
YG1
7-0
Description
Y gain, 8 lsbs.
Bottom 8 bits of the luma gain
lsb = 1/256
DPC
000
001
010
011
100
101
110
111
Function
Reserved
TMC22051A
TMC22052A
TMC22053A
Reserved
TMC22151A
TMC22152A
TMC22153A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMC22052AKHC | Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
| TMC22053AKHC | Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
| TMC22151AKHC | Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
| TMC22152AKHC | Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
| TMC22153AKHC | JT 32C 32#20 SKT PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2302A | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AH5C | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC2302AH5C1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC2302AKEC | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AKEC1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
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