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參數(shù)資料
| 型號(hào)： | TMC22X5YA |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
| 中文描述： | 多標(biāo)準(zhǔn)數(shù)字視頻解碼器三線自適應(yīng)梳狀解碼器系列，8 |
| 文件頁(yè)數(shù)： | 26/84頁(yè) |
| 文件大?。?/td> | 417K |
| 代理商： | TMC22X5YA |
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TMC22x5yA
PRODUCT SPECIFICATION
26
REV. 1.0.0 2/4/03
Control Register De
fi
nitions
(continued)
Buffered register set 0 (17)
Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
SG0
7
SG0
6
SG0
5
SG0
4
SG0
3
SG0
2
SG0
1
SG0
0
Reg
17
Bit
7-0
Name
SG0
7-0
Description
Msync gain, 8 lsbs.
Bottom 8 bits of mixed sync scalar
lsb = 1/256
Buffered register set 0 (18)
Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
YG0
7
YG0
6
YG0
5
YG0
4
YG0
3
YG0
2
YG0
1
YG0
0
Reg
18
Bit
7-0
Name
YG0
7-0
Description
Y gain, 8 lsbs.
Bottom 8 bits of the luma gain
lsb = 1/256
Buffered register set 0 (19)
Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
UG0
7
UG0
6
UG0
5
UG0
4
UG0
3
UG0
2
UG0
1
UG0
0
Reg
19
Bit
7-0
Name
UG0
7-0
Description
U gain, 8 lsbs.
Bottom 8 bits of the U gain
lsb = 1/256
Buffered register set 0 (1A)
Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
VG0
7
VG0
6
VG0
5
VG0
4
VG0
3
VG0
2
VG0
1
VG0
0
Reg
1A
Bit
7-0
Name
VG0
7-0
Description
V gain, 8 lsbs.
Bottom 8 bits of the V gain
lsb = 1/256
Buffered register set 0 (1B)
Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
YG0
9
YG0
8
UG0
10
UG0
9
UG0
8
Reserved
VG0
9
VG0
8
Reg
1B
1B
1B
1B
Bit
7-6
5-3
2
1-0
Name
YG0
9-8
UG0
10-8
Reserved
VG0
9-8
Description
Y gain, 2 msb.
Top 2 bits of the Y gain. msb = 2
U gain, 3 msbs.
Top 3 bits of the U gain. msb = 4
Reserved, set to zero.
V gain, 2 msbs.
Top 2 bits of the V gain. msb = 2
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