參數(shù)資料
型號(hào)： TMC22X5YA
廠商： Fairchild Semiconductor Corporation
英文描述： Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit
中文描述： 多標(biāo)準(zhǔn)數(shù)字視頻解碼器三線自適應(yīng)梳狀解碼器系列，8
文件頁(yè)數(shù)： 27/84頁(yè)
文件大小： 417K
代理商： TMC22X5YA
PRODUCT SPECIFICATION
TMC22x5yA
REV. 1.0.0 2/4/03
27
Control Register De
fi
nitions
(continued)
Buffered register set 0 (1C)
Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
YOFF0
7
YOFF0
6
YOFF0
5
YOFF0
4
YOFF0
3
YOFF0
2
YOFF0
1
YOFF0
0
Reg
1C
Bit
7-0
Name
YOFF0
7-0
Description
Y offset, 8 lsbs.
Bottom 8 bits of luma or RGB offset
Buffered register set 0 (1D)
Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
Reserved
YOFF0
8
SG0
9
SG0
8
Reg
1D
1D
1D
Bit
7-3
2
1-0
Name
Reserved
YOFF0
8
SG0
9-8
Description
Reserved, set to zero.
Y offset, msb.
msb of YOFF
Msync gain, 2 msbs.
Top 2 bits of mixed sync scalar.
msb = 2
Buffered register set 0 (1E)
Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
SYSPH0
6
SYSPH0
5
SYSPH0
4
SYSPH0
3
SYSPH0
2
SYSPH0
1
SYSPH0
0
VAXIS0
Reg
1E
1E
Bit
7-1
0
Name
SYSPH0
6-0
VAXIS0
Description
7 lsbs of phase offset.
Bottom 7 bits of the 15 bit system phase offset
V axis flip.
Flips the sign of the V axis when HIGH.
Buffered register set 0 (1F)
Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
SYSPH0
14
SYSPH0
13
SYSPH0
12
SYSPH0
11
SYSPH0
10
SYSPH0
9
SYSPH0
8
SYSPH0
7
Reg
1F
Bit
7-0
Name
SYSPH014-7
Description
8 msbs of phase offset.
Top 8 bits of 15 bit system phase offset.
Normalized Subcarrier Frequency (20)
7
6
5
4
3
2
1
0
FSC
3
FSC
2
FSC
1
FSC
0
Reserved
Reg
20
20
Bit
7-4
3-0
Name
FSC
3-0
Reserved
Description
Bottom 4 bits of fsc.
Bottom 4 bits of the 28 bit subcarrier SEED
Reserved, set to zero.
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