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參數(shù)資料
| 型號： | TMC22X5YA |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
| 中文描述： | 多標(biāo)準(zhǔn)數(shù)字視頻解碼器三線自適應(yīng)梳狀解碼器系列，8 |
| 文件頁數(shù)： | 29/84頁 |
| 文件大?。?/td> | 417K |
| 代理商： | TMC22X5YA |
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PRODUCT SPECIFICATION
TMC22x5yA
REV. 1.0.0 2/4/03
29
Control Register De
fi
nitions
(continued)
Normalized Subcarrier Frequency (24)
7
6
5
4
3
2
1
0
CLMPEN
PFLTEN
CLPSEL
1-0
CLPBY
CLPOF
2-0
Reg
24
Bit
7
Name
DREFSEL
Description
Decoder Reference Signal Select.
When HIGH, enables a negative going
clamp pulse on the DREF pin. The position of the clamp pulse is controlled
by register 24. When LOW the DREF pin is HIGH during the active video
portion of each line and LOW during the horizontal and vertical blanking
intervals.
Phase error filter bypass.
When HIGH, no filtering is done on the phase
error signals for the comb filter adapter. When LOW, the filter is enabled.
Internal black level clamp selection.
24
6
PFLTBY
24
5-4
CLPSEL
1-0
24
3
VCLPEN
Vertical clamp filter enable.
When LOW, vertical clamp filter is disabled.
When HIGH, vertical clamp filter is enabled.
Clamp guard band.
When an error value between two consecutive lines
black level is less than the guard band, it does not effect the filtered black
level.
24
2-0
BAND
2-0
Normalized Subcarrier Frequency (25)
7
6
5
4
3
2
1
0
CPDLY
7-0
Reg
25
Bit
7-0
Name
CPDLY
7-0
Description
Clamp pulse delay.
Controls the number of clock cycles from hsync before
the 0.5
μ
Sec clamp pulse is output to the AVOUT pin. This option is only
enabled when register 24 bit 7 is set HIGH.
CLMP[1:0]
00
01
10
Function
Clamp disabled, black level set to 240
Clamp disabled, black level set to 256
Clamp enabled, use Delayed VIDEOB input as
reference
Clamp enabled, use LPF as reference
11
BANDS[2:0]
000
001
010
011
100
101
110
111
Function
No guard band
error value < 2
error value < 4
error value < 6
error value < 8
error value < 10
error value < 12
error value < 15
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